Valero Bresó, A.; Sahuquillo Borrás, J.; Lorente Garcés, VJ.; Petit Martí, SV.; López Rodríguez, PJ.; Duato Marín, JF. (2012). Impact on performance and energy of the retention time and processor frequency in L1 macrocell-based data caches. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20(6):1108-1117. https://doi.org/10.1109/TVLSI.2011.2142202
Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/34853
Title: | Impact on performance and energy of the retention time and processor frequency in L1 macrocell-based data caches | |
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[EN] Cache memories dissipate an important amount of the energy budget in current microprocessors. This is mainly due to cache cells are typically implemented with six transistors. To tackle this design concern, recent ...[+]
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Copyrigths: | Reserva de todos los derechos | |
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Publisher version: | http://dx.doi.org/10.1109/TVLSI.2011.2142202 | |
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This work was supported in part by Spanish CICYT under Grant TIN2009-14475-C04-01, by Consolider-Ingenio 2010 under Grant CSD2006-00046, and by European community’s Seventh Framework Programme (FP7/2007-2013) under Grant 289154.[+]
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