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Impact on performance and energy of the retention time and processor frequency in L1 macrocell-based data caches

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Impact on performance and energy of the retention time and processor frequency in L1 macrocell-based data caches

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dc.contributor.author Valero Bresó, Alejandro es_ES
dc.contributor.author Sahuquillo Borrás, Julio es_ES
dc.contributor.author Lorente Garcés, Vicente Jesús es_ES
dc.contributor.author Petit Martí, Salvador Vicente es_ES
dc.contributor.author López Rodríguez, Pedro Juan es_ES
dc.contributor.author Duato Marín, José Francisco es_ES
dc.date.accessioned 2014-01-10T13:49:38Z
dc.date.issued 2012-06
dc.identifier.issn 1063-8210
dc.identifier.uri http://hdl.handle.net/10251/34853
dc.description.abstract [EN] Cache memories dissipate an important amount of the energy budget in current microprocessors. This is mainly due to cache cells are typically implemented with six transistors. To tackle this design concern, recent research has focused on the proposal of new cache cells. An n-bit cache cell, namely macrocell, has been proposed in a previous work. This cell combines SRAM and eDRAM technologies with the aim of reducing energy consumption while maintaining the performance. The capacitance of eDRAM cells impacts on energy consumption and performance since these cells lose their state once the retention time expires. On such a case, data must be fetched from a lower level of the memory hierarchy, so negatively impacting on performance and energy consumption. As opposite, if the capacitance is too high, energy would be wasted without bringing performance benefits. This paper identifies the optimal capacitance for a given processor frequency. To this end, the tradeoff between performance and energy consumption of a macrocell-based cache has been evaluated varying the capacitance and frequency. Experimental results show that, compared to a conventional cache, performance losses are lower than 2% and energy savings are up to 55% for a cache with 10 fF capacitors and frequencies higher than 1 GHz. In addition, using trench capacitors, a 4-bit macrocell reduces by 29% the area of four conventional SRAM cells. es_ES
dc.description.sponsorship This work was supported in part by Spanish CICYT under Grant TIN2009-14475-C04-01, by Consolider-Ingenio 2010 under Grant CSD2006-00046, and by European community’s Seventh Framework Programme (FP7/2007-2013) under Grant 289154.
dc.format.extent 11 es_ES
dc.language Inglés es_ES
dc.publisher Institute of Electrical and Electronics Engineers (IEEE) es_ES
dc.relation CICYT/TIN2009-14475-C04-01 es_ES
dc.relation CICYT/CONSOLIDER-INGENIO/CSD2006-00046 es_ES
dc.relation.ispartof IEEE Transactions on Very Large Scale Integration (VLSI) Systems es_ES
dc.rights Reserva de todos los derechos es_ES
dc.subject Edram memory cells es_ES
dc.subject Edram capacitance es_ES
dc.subject Energy consumption es_ES
dc.subject Retention time es_ES
dc.subject Sram memory cells es_ES
dc.subject.classification ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES es_ES
dc.title Impact on performance and energy of the retention time and processor frequency in L1 macrocell-based data caches es_ES
dc.type Artículo es_ES
dc.embargo.lift 10000-01-01
dc.embargo.terms forever es_ES
dc.identifier.doi 10.1109/TVLSI.2011.2142202
dc.relation.projectID info:eu-repo/grantAgreement/EC/FP7/289154/EU
dc.rights.accessRights Abierto es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors es_ES
dc.description.bibliographicCitation Valero Bresó, A.; Sahuquillo Borrás, J.; Lorente Garcés, VJ.; Petit Martí, SV.; López Rodríguez, PJ.; Duato Marín, JF. (2012). Impact on performance and energy of the retention time and processor frequency in L1 macrocell-based data caches. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20(6):1108-1117. https://doi.org/10.1109/TVLSI.2011.2142202 es_ES
dc.description.accrualMethod S es_ES
dc.relation.publisherversion http://dx.doi.org/10.1109/TVLSI.2011.2142202 es_ES
dc.description.upvformatpinicio 1108 es_ES
dc.description.upvformatpfin 1117 es_ES
dc.type.version info:eu-repo/semantics/publishedVersion es_ES
dc.description.volume 20 es_ES
dc.description.issue 6 es_ES
dc.relation.senia 234036
dc.contributor.funder Comisión Interministerial de Ciencia y Tecnología
dc.contributor.funder European Commission


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