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Low cost hardware implementation of logarithm approximation

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Low cost hardware implementation of logarithm approximation

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Gutiérrez Mazón, R.; Valls Coquillat, J. (2011). Low cost hardware implementation of logarithm approximation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19(12):2326-2330. doi:10.1109/TVLSI.2010.2081387

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/35461

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Title: Low cost hardware implementation of logarithm approximation
Author:
UPV Unit: Universitat Politècnica de València. Departamento de Ingeniería Electrónica - Departament d'Enginyeria Electrònica
Universitat Politècnica de València. Instituto Universitario de Telecomunicación y Aplicaciones Multimedia - Institut Universitari de Telecomunicacions i Aplicacions Multimèdia
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Abstract:
A low cost, high-speed architecture for the computation of the binary logarithm is proposed. It is based on the Mitchell approximation with two correction stages: a piecewise linear interpolation with power-of-two slopes ...[+]
Subjects: Logarithm approximation , Mitchell's error correction , Piecewise linear approximation
Copyrigths: Cerrado
Source:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. (issn: 1063-8210 )
DOI: 10.1109/TVLSI.2010.2081387
Publisher:
Institute of Electrical and Electronics Engineers (IEEE)
Publisher version: http://dx.doi.org/10.1109/TVLSI.2010.2081387
Thanks:
This research was supported by FEDER, the Spanish Ministerio de Ciencia e Innovacion, under Grant No. TEC2008-06787.
Type: Artículo

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