- -

Low cost hardware implementation of logarithm approximation

RiuNet: Institutional repository of the Polithecnic University of Valencia

Share/Send to

Cited by

Statistics

Low cost hardware implementation of logarithm approximation

Show simple item record

Files in this item

dc.contributor.author Gutiérrez Mazón, Roberto es_ES
dc.contributor.author Valls Coquillat, Javier es_ES
dc.date.accessioned 2014-02-10T19:19:24Z
dc.date.issued 2011-12
dc.identifier.issn 1063-8210
dc.identifier.uri http://hdl.handle.net/10251/35461
dc.description.abstract A low cost, high-speed architecture for the computation of the binary logarithm is proposed. It is based on the Mitchell approximation with two correction stages: a piecewise linear interpolation with power-of-two slopes and truncated mantissa, and a LUT-based correction stage that correct the piecewise interpolation error. The architecture has been implemented in an FPGA device and the results are compared with other low cost architectures requiring less area and achieving high-speed. © 2006 IEEE. es_ES
dc.description.sponsorship This research was supported by FEDER, the Spanish Ministerio de Ciencia e Innovacion, under Grant No. TEC2008-06787. en_EN
dc.format.extent 5 es_ES
dc.language Inglés es_ES
dc.publisher Institute of Electrical and Electronics Engineers (IEEE) es_ES
dc.relation FEDER, the Spanish Ministerio de Ciencia e Innovacion [TEC2008-06787] es_ES
dc.relation.ispartof IEEE Transactions on Very Large Scale Integration (VLSI) Systems es_ES
dc.rights Reserva de todos los derechos es_ES
dc.subject Logarithm approximation es_ES
dc.subject Mitchell's error correction es_ES
dc.subject Piecewise linear approximation es_ES
dc.subject.classification TECNOLOGIA ELECTRONICA es_ES
dc.title Low cost hardware implementation of logarithm approximation es_ES
dc.type Artículo es_ES
dc.embargo.lift 10000-01-01
dc.embargo.terms forever es_ES
dc.identifier.doi 10.1109/TVLSI.2010.2081387
dc.rights.accessRights Cerrado es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Ingeniería Electrónica - Departament d'Enginyeria Electrònica es_ES
dc.contributor.affiliation Universitat Politècnica de València. Instituto Universitario de Telecomunicación y Aplicaciones Multimedia - Institut Universitari de Telecomunicacions i Aplicacions Multimèdia es_ES
dc.description.bibliographicCitation Gutiérrez Mazón, R.; Valls Coquillat, J. (2011). Low cost hardware implementation of logarithm approximation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19(12):2326-2330. doi:10.1109/TVLSI.2010.2081387 es_ES
dc.description.accrualMethod Senia es_ES
dc.relation.publisherversion http://dx.doi.org/10.1109/TVLSI.2010.2081387 es_ES
dc.description.upvformatpinicio 2326 es_ES
dc.description.upvformatpfin 2330 es_ES
dc.type.version info:eu repo/semantics/publishedVersion es_ES
dc.description.volume 19 es_ES
dc.description.issue 12 es_ES
dc.relation.senia 210719


This item appears in the following Collection(s)

Show simple item record