Mostrar el registro sencillo del ítem
dc.contributor.author | Angarita Preciado, Fabián Enrique | es_ES |
dc.contributor.author | Marín-Roig Ramón, José | es_ES |
dc.contributor.author | Almenar Terré, Vicenç | es_ES |
dc.contributor.author | Valls Coquillat, Javier | es_ES |
dc.date.accessioned | 2014-02-17T15:45:42Z | |
dc.date.issued | 2012-11-06 | |
dc.identifier.issn | 1751-8628 | |
dc.identifier.uri | http://hdl.handle.net/10251/35734 | |
dc.description.abstract | This study proposes a new low-complexity decoding algorithm for low-density parity check codes, which is a variation of the offset min-sum algorithm and achieves a similar performance with lower hardware cost. A finite precision study is presented and the hardware cost of the implementation of three very large scale integration architectures is evaluated. As a conclusion, the proposed algorithm achieves similar performance with an area saving of around 18, 10 and 14% for the memory-based partially parallel, fully parallel and sliced message passing implementations, respectively. | es_ES |
dc.description.sponsorship | This research was supported by Fondo Europeo de Desarrollo Regional (FEDER), the Spanish Ministerio de Ciencia e Innovacion, under grant numbers TEC2008-06787 and TEC2011-27916. | en_EN |
dc.format.extent | 7 | es_ES |
dc.language | Inglés | es_ES |
dc.publisher | Institution of Engineering and Technology (IET) | es_ES |
dc.relation.ispartof | IET Communications | es_ES |
dc.rights | Reserva de todos los derechos | es_ES |
dc.subject | LDPC CODES | es_ES |
dc.subject | VLSI | es_ES |
dc.subject | Decoding | es_ES |
dc.subject | Message passing | es_ES |
dc.subject | Parity check codes | es_ES |
dc.subject.classification | TECNOLOGIA ELECTRONICA | es_ES |
dc.subject.classification | TEORIA DE LA SEÑAL Y COMUNICACIONES | es_ES |
dc.title | Low-complexity low-density parity check decoding algorithm for high-speed very large scale integration implementation | es_ES |
dc.type | Artículo | es_ES |
dc.embargo.lift | 10000-01-01 | |
dc.embargo.terms | forever | es_ES |
dc.identifier.doi | 10.1049/iet-com.2011.0542 | |
dc.relation.projectID | info:eu-repo/grantAgreement/MICINN//TEC2008-06787/ES/ARQUITECTURAS DE FEC PARA SISTEMAS DE COMUNICACIONES DE MUY ALTA VELOCIDAD/ | |
dc.relation.projectID | info:eu-repo/grantAgreement/MICINN//TEC2011-27916/ES/ALGORITMOS Y ARQUITECTURAS DE FEC PARA FUTUROS SISTEMAS DE COMUNICACIONES/ | |
dc.rights.accessRights | Cerrado | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Instituto Universitario de Telecomunicación y Aplicaciones Multimedia - Institut Universitari de Telecomunicacions i Aplicacions Multimèdia | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Departamento de Ingeniería Electrónica - Departament d'Enginyeria Electrònica | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Departamento de Comunicaciones - Departament de Comunicacions | es_ES |
dc.description.bibliographicCitation | Angarita Preciado, FE.; Marín-Roig Ramón, J.; Almenar Terré, V.; Valls Coquillat, J. (2012). Low-complexity low-density parity check decoding algorithm for high-speed very large scale integration implementation. IET Communications. 6(16):2575-2581. https://doi.org/10.1049/iet-com.2011.0542 | es_ES |
dc.description.accrualMethod | S | es_ES |
dc.relation.publisherversion | http://dx.doi.org/10.1049/iet-com.2011.0542 | es_ES |
dc.description.upvformatpinicio | 2575 | es_ES |
dc.description.upvformatpfin | 2581 | es_ES |
dc.type.version | info:eu-repo/semantics/publishedVersion | es_ES |
dc.description.volume | 6 | es_ES |
dc.description.issue | 16 | es_ES |
dc.relation.senia | 232516 | |
dc.contributor.funder | European Regional Development Fund | |
dc.contributor.funder | Ministerio de Ciencia e Innovación |