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A dynamic power-aware partitioner with task migration for multicore embedded systems

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A dynamic power-aware partitioner with task migration for multicore embedded systems

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dc.contributor.author March Cabrelles, José Luis es_ES
dc.contributor.author Sahuquillo Borrás, Julio es_ES
dc.contributor.author Petit Martí, Salvador Vicente es_ES
dc.contributor.author Hassan Mohamed, Houcine es_ES
dc.contributor.author Duato Marín, José Francisco es_ES
dc.date.accessioned 2014-02-20T08:00:10Z
dc.date.issued 2011
dc.identifier.isbn 978-3-642-23399-9
dc.identifier.issn 0302-9743
dc.identifier.uri http://hdl.handle.net/10251/35796
dc.description.abstract Nowadays, a key design issue in embedded systems is how to reduce the power consumption, since batteries have a limited energy budget. For this purpose, several techniques such as Dynamic Voltage Scaling (DVS) or task migration can be used. DVS allows reducing power by selecting the optimal voltage supply, while task migration achieves this effect by balancing the workload among cores. This paper first analyzes the impact on energy due to task migration in multicore embedded systems with DVS capability and using the well-known Worst Fit (WF) partitioning heuristic. To reduce overhead, migrations are only performed at the time that a task arrives to and/or leaves the system and, in such a case, only one migration is allowed. The huge potential on energy saving due to task migration, leads us to propose a new dynamic partitioner, namely DP, that migrates tasks in a more efficient way than typical partitioners. Unlike WF, the proposed algorithm examines which is the optimal target core before allowing a migration. Experimental results show that DP can improve energy consumption in a factor up to 2.74 over the typical WF algorithm. © 2011 Springer-Verlag. es_ES
dc.format.extent 12 es_ES
dc.language Inglés es_ES
dc.publisher Springer Verlag (Germany) es_ES
dc.relation Spanish CICYT [TIN2009-14475-C04-01] es_ES
dc.relation Consolider-Ingenio [CSD2006-00046] es_ES
dc.relation.ispartof Euro-Par 2011 Parallel Processing es_ES
dc.relation.ispartofseries Lecture Notes in Computer Science;vol. 6852
dc.rights Reserva de todos los derechos es_ES
dc.subject Design issues es_ES
dc.subject Dynamic voltage scaling es_ES
dc.subject Energy budgets es_ES
dc.subject Multicore embedded system es_ES
dc.subject Optimal target es_ES
dc.subject Power-aware es_ES
dc.subject Reducing power es_ES
dc.subject Task migration es_ES
dc.subject Voltage supply es_ES
dc.subject.classification ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES es_ES
dc.title A dynamic power-aware partitioner with task migration for multicore embedded systems es_ES
dc.type Capítulo de libro es_ES
dc.embargo.lift 10000-01-01
dc.embargo.terms forever es_ES
dc.identifier.doi 10.1007/978-3-642-23400-2_21
dc.relation.projectID info:eu-repo/grantAgreement/EC/FP7/217068/EU en_EN
dc.rights.accessRights Abierto es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors es_ES
dc.description.bibliographicCitation March Cabrelles, JL.; Sahuquillo Borrás, J.; Petit Martí, SV.; Hassan Mohamed, H.; Duato Marín, JF. (2011). A dynamic power-aware partitioner with task migration for multicore embedded systems. En Euro-Par 2011 Parallel Processing. Springer Verlag (Germany). 2011(6852):218-229. doi:10.1007/978-3-642-23400-2_21 es_ES
dc.description.accrualMethod Senia es_ES
dc.relation.conferencename 17th International Conference, Euro-Par 2011 es_ES
dc.relation.conferencedate August 29 - September 2, 2011 es_ES
dc.relation.conferenceplace Bordeaux, France es_ES
dc.relation.publisherversion http://link.springer.com/chapter/10.1007/978-3-642-23400-2_21 es_ES
dc.description.upvformatpinicio 218 es_ES
dc.description.upvformatpfin 229 es_ES
dc.type.version info:eu repo/semantics/publishedVersion es_ES
dc.description.volume 2011 es_ES
dc.description.issue 6852 es_ES
dc.relation.senia 208083


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