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Fault-tolerant vertical link design for effective 3D stacking

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Fault-tolerant vertical link design for effective 3D stacking

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Hernández Luz, C.; Roca Pérez, A.; Flich Cardo, J.; Silla Jiménez, F.; Duato Marín, JF. (2011). Fault-tolerant vertical link design for effective 3D stacking. IEEE Computer Architecture Letters. 10(2):41-44. https://doi.org/10.1109/L-CA.2011.17

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/35905

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Title: Fault-tolerant vertical link design for effective 3D stacking
Author: Hernández Luz, Carles Roca Pérez, Antoni Flich Cardo, José Silla Jiménez, Federico Duato Marín, José Francisco
UPV Unit: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Issued date:
Abstract:
[EN] Recently, 3D stacking has been proposed to alleviate the memory bandwidth limitation arising in chip multiprocessors (CMPs). As the number of integrated cores in the chip increases the access to external memory becomes ...[+]
Subjects: 3D Stacking , NoC , Fault Tolerance
Copyrigths: Reserva de todos los derechos
Source:
IEEE Computer Architecture Letters. (issn: 1556-6056 )
DOI: 10.1109/L-CA.2011.17
Publisher:
Institute of Electrical and Electronics Engineers (IEEE)
Publisher version: http://dx.doi.org/10.1109/L-CA.2011.17
Project ID: info:eu-repo/grantAgreement/EC/FP7/248972
Thanks:
This work was supported by the Spanish MEC and MICINN, as well as European Comission FEDER funds, under Grants CSD2006-00046 and TIN2009-14475-C04. It was also partly supported by the project NaNoC (project label 248972) ...[+]
Type: Artículo

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