Roca Pérez, A.; Flich Cardo, J.; Silla Jiménez, F.; Duato Marín, JF. (2011). A low-latency modular switch for CMP systems. Microprocessors and Microsystems. 35(8):742-754. https://doi.org/10.1016/j.micpro.2011.08.011
Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/35968
Title:
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A low-latency modular switch for CMP systems
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Author:
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Roca Pérez, Antoni
Flich Cardo, José
Silla Jiménez, Federico
Duato Marín, José Francisco
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UPV Unit:
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Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
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Issued date:
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Abstract:
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[EN] As technology advances, the number of cores in Chip MultiProcessor systems and MultiProcessor Systems-on-Chips keeps increasing. The network must provide sustained throughput and ultra-low latencies. In this paper we ...[+]
[EN] As technology advances, the number of cores in Chip MultiProcessor systems and MultiProcessor Systems-on-Chips keeps increasing. The network must provide sustained throughput and ultra-low latencies. In this paper we propose new pipelined switch designs focused in reducing the switch latency. We identify the switch components that limit the switch frequency: the arbiter. Then, we simplify the arbiter logic by using multiple smaller arbiters, but increasing greatly the switch area. To solve this problem, a second design is presented where the routing traversal and arbitrations tasks are mixed. Results demonstrate a switch latency reduction ranging from 10% to 21%. Network latency is reduced in a range from 11% to 15%. © 2011 Elsevier B.V. All rights reserved.
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Subjects:
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Arbitration implementation
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Network-on-chip
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Switch design
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Copyrigths:
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Reserva de todos los derechos
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Source:
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Microprocessors and Microsystems. (issn:
0141-9331
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DOI:
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10.1016/j.micpro.2011.08.011
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Publisher:
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Elsevier
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Publisher version:
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http://dx.doi.org/10.1016/j.micpro.2011.08.011
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Project ID:
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info:eu-repo/grantAgreement/EC/FP7/248972/EU/Nanoscale Silicon-Aware Network-on-Chip Design Platform/
info:eu-repo/grantAgreement/MEC//CSD2006-00046/ES/Arquitecturas fiables y de altas prestaciones para centros de proceso de datos y servidores de Internet/
info:eu-repo/grantAgreement/MICINN//TIN2009-14475-C04-01/ES/Arquitecturas De Servidores, Aplicaciones Y Servicios/
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Thanks:
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This work was supported by the Spanish MEC and MICINN, as well as European Commission FEDER funds, under Grants CSD2006-00046 and TIN2009-14475-C04. It was also partly supported by the project NaNoC (Project Label 248972) ...[+]
This work was supported by the Spanish MEC and MICINN, as well as European Commission FEDER funds, under Grants CSD2006-00046 and TIN2009-14475-C04. It was also partly supported by the project NaNoC (Project Label 248972) which is funded by the European Commission within the Research Programme FP7.
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Type:
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Artículo
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