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dc.contributor.author | Roca Pérez, Antoni | es_ES |
dc.contributor.author | Flich Cardo, José | es_ES |
dc.contributor.author | Silla Jiménez, Federico | es_ES |
dc.contributor.author | Duato Marín, José Francisco | es_ES |
dc.date.accessioned | 2014-02-25T16:36:35Z | |
dc.date.issued | 2011-11 | |
dc.identifier.issn | 0141-9331 | |
dc.identifier.uri | http://hdl.handle.net/10251/35968 | |
dc.description.abstract | [EN] As technology advances, the number of cores in Chip MultiProcessor systems and MultiProcessor Systems-on-Chips keeps increasing. The network must provide sustained throughput and ultra-low latencies. In this paper we propose new pipelined switch designs focused in reducing the switch latency. We identify the switch components that limit the switch frequency: the arbiter. Then, we simplify the arbiter logic by using multiple smaller arbiters, but increasing greatly the switch area. To solve this problem, a second design is presented where the routing traversal and arbitrations tasks are mixed. Results demonstrate a switch latency reduction ranging from 10% to 21%. Network latency is reduced in a range from 11% to 15%. © 2011 Elsevier B.V. All rights reserved. | es_ES |
dc.description.sponsorship | This work was supported by the Spanish MEC and MICINN, as well as European Commission FEDER funds, under Grants CSD2006-00046 and TIN2009-14475-C04. It was also partly supported by the project NaNoC (Project Label 248972) which is funded by the European Commission within the Research Programme FP7. | en_EN |
dc.format.extent | 13 | es_ES |
dc.language | Inglés | es_ES |
dc.publisher | Elsevier | es_ES |
dc.relation.ispartof | Microprocessors and Microsystems | es_ES |
dc.rights | Reserva de todos los derechos | es_ES |
dc.subject | Arbitration implementation | es_ES |
dc.subject | Network-on-chip | es_ES |
dc.subject | Switch design | es_ES |
dc.subject.classification | ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES | es_ES |
dc.title | A low-latency modular switch for CMP systems | es_ES |
dc.type | Artículo | es_ES |
dc.embargo.lift | 10000-01-01 | |
dc.embargo.terms | forever | es_ES |
dc.identifier.doi | 10.1016/j.micpro.2011.08.011 | |
dc.relation.projectID | info:eu-repo/grantAgreement/EC/FP7/248972/EU/Nanoscale Silicon-Aware Network-on-Chip Design Platform/ | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/MEC//CSD2006-00046/ES/Arquitecturas fiables y de altas prestaciones para centros de proceso de datos y servidores de Internet/ | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/MICINN//TIN2009-14475-C04-01/ES/Arquitecturas De Servidores, Aplicaciones Y Servicios/ | es_ES |
dc.rights.accessRights | Abierto | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors | es_ES |
dc.description.bibliographicCitation | Roca Pérez, A.; Flich Cardo, J.; Silla Jiménez, F.; Duato Marín, JF. (2011). A low-latency modular switch for CMP systems. Microprocessors and Microsystems. 35(8):742-754. https://doi.org/10.1016/j.micpro.2011.08.011 | es_ES |
dc.description.accrualMethod | S | es_ES |
dc.relation.publisherversion | http://dx.doi.org/10.1016/j.micpro.2011.08.011 | es_ES |
dc.description.upvformatpinicio | 742 | es_ES |
dc.description.upvformatpfin | 754 | es_ES |
dc.type.version | info:eu-repo/semantics/publishedVersion | es_ES |
dc.description.volume | 35 | es_ES |
dc.description.issue | 8 | es_ES |
dc.relation.senia | 207225 | |
dc.contributor.funder | European Commission | |
dc.contributor.funder | Ministerio de Ciencia e Innovación | |
dc.contributor.funder | Ministerio de Educación y Ciencia | es_ES |