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A Sequentially Consistent Multiprocessor Architecture for Out-of-Order Retirement of Instructions

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A Sequentially Consistent Multiprocessor Architecture for Out-of-Order Retirement of Instructions

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Ubal Tena, R.; Sahuquillo Borrás, J.; Petit Martí, SV.; López Rodríguez, PJ.; Kaeli, D. (2012). A Sequentially Consistent Multiprocessor Architecture for Out-of-Order Retirement of Instructions. IEEE Transactions on Parallel and Distributed Systems. 23(8):1361-1368. doi:10.1109/TPDS.2011.255

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/36007

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Title: A Sequentially Consistent Multiprocessor Architecture for Out-of-Order Retirement of Instructions
Author:
UPV Unit: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Issued date:
Abstract:
Out-of-order retirement of instructions has been shown to be an effective technique to increase the number of in-flight instructions. This form of runtime scheduling can reduce pipeline stalls caused by head-of-line blocking ...[+]
Subjects: Out-of-order retirement , Multicore processors , Validation buffer , Sequential consistency
Copyrigths: Reserva de todos los derechos
Source:
IEEE Transactions on Parallel and Distributed Systems. (issn: 1045-9219 )
DOI: 10.1109/TPDS.2011.255
Publisher:
Institute of Electrical and Electronics Engineers (IEEE)
Publisher version: http://dx.dor.org/:10.1109/TPDS.2011.255
Type: Artículo

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