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A Sequentially Consistent Multiprocessor Architecture for Out-of-Order Retirement of Instructions

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A Sequentially Consistent Multiprocessor Architecture for Out-of-Order Retirement of Instructions

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dc.contributor.author Ubal Tena, Rafael es_ES
dc.contributor.author Sahuquillo Borrás, Julio es_ES
dc.contributor.author Petit Martí, Salvador Vicente es_ES
dc.contributor.author López Rodríguez, Pedro Juan es_ES
dc.contributor.author Kaeli, David es_ES
dc.date.accessioned 2014-02-27T11:32:53Z
dc.date.issued 2012-08
dc.identifier.issn 1045-9219
dc.identifier.uri http://hdl.handle.net/10251/36007
dc.description.abstract Out-of-order retirement of instructions has been shown to be an effective technique to increase the number of in-flight instructions. This form of runtime scheduling can reduce pipeline stalls caused by head-of-line blocking effects in the reorder buffer (ROB). Expanding the width of the instruction window can be highly beneficial to multiprocessors that implement a strict memory model, especially when both loads and stores encounter long latencies due to cache misses, and whose stalls must be overlapped with instruction execution to overcome the memory latencies. Based on the Validation Buffer (VB) architecture (a previously proposed out- of-order retirement, checkpoint-free architecture for single processors), this paper proposes a cost-effective, scalable, out-of-order retirement multiprocessor, capable of enforcing sequential consistency without impacting the design of the memory hierarchy or interconnect. Our simulation results indicate that utilizing a VB can speed up both relaxed and sequentially consistent in-order retirement in future multiprocessor systems by between 3 and 20 percent, depending on the ROB size. es_ES
dc.format.extent 8 es_ES
dc.language Inglés es_ES
dc.publisher Institute of Electrical and Electronics Engineers (IEEE) es_ES
dc.relation.ispartof IEEE Transactions on Parallel and Distributed Systems es_ES
dc.rights Reserva de todos los derechos es_ES
dc.subject Out-of-order retirement es_ES
dc.subject Multicore processors es_ES
dc.subject Validation buffer es_ES
dc.subject Sequential consistency es_ES
dc.subject.classification ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES es_ES
dc.title A Sequentially Consistent Multiprocessor Architecture for Out-of-Order Retirement of Instructions es_ES
dc.type Artículo es_ES
dc.embargo.lift 10000-01-01
dc.embargo.terms forever es_ES
dc.identifier.doi 10.1109/TPDS.2011.255
dc.rights.accessRights Abierto es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors es_ES
dc.description.bibliographicCitation Ubal Tena, R.; Sahuquillo Borrás, J.; Petit Martí, SV.; López Rodríguez, PJ.; Kaeli, D. (2012). A Sequentially Consistent Multiprocessor Architecture for Out-of-Order Retirement of Instructions. IEEE Transactions on Parallel and Distributed Systems. 23(8):1361-1368. doi:10.1109/TPDS.2011.255 es_ES
dc.description.accrualMethod S es_ES
dc.relation.publisherversion http://dx.dor.org/:10.1109/TPDS.2011.255 es_ES
dc.description.upvformatpinicio 1361 es_ES
dc.description.upvformatpfin 1368 es_ES
dc.type.version info:eu-repo/semantics/publishedVersion es_ES
dc.description.volume 23 es_ES
dc.description.issue 8 es_ES
dc.relation.senia 236589


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