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Design, performance, and energy consumption of eDRAM/SRAM macrocells for L1 data caches

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Design, performance, and energy consumption of eDRAM/SRAM macrocells for L1 data caches

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Valero Bresó, A.; Petit Martí, SV.; Sahuquillo Borrás, J.; López Rodríguez, PJ.; Duato Marín, JF. (2012). Design, performance, and energy consumption of eDRAM/SRAM macrocells for L1 data caches. IEEE Transactions on Computers. 61(9):1231-1242. doi:10.1109/TC.2011.138

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Title: Design, performance, and energy consumption of eDRAM/SRAM macrocells for L1 data caches
Author:
UPV Unit: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Issued date:
Abstract:
SRAM and DRAM have been the predominant technologies used to implement memory cells in computer systems, each one having its advantages and shortcomings. SRAM cells are faster and require no refresh since reads are not ...[+]
Subjects: Retention time , Static and dynamic energy , Static and dynamic memory cells , Way prediction
Copyrigths: Reserva de todos los derechos
Source:
IEEE Transactions on Computers. (issn: 0018-9340 )
DOI: 10.1109/TC.2011.138
Publisher:
Institute of Electrical and Electronics Engineers (IEEE)
Publisher version: http://dx.doi.org/10.1109/TC.2011.138
Description: (c) 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works
Thanks:
This work was supported by the Spanish Ministerio de Ciencia e Innovacion (MICINN), and jointly financed with Plan E funds under Grant TIN2009-14475-C04-01 and by Consolider-Ingenio 2010 under Grant CSD2006-00046.
Type: Artículo

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