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Design, performance, and energy consumption of eDRAM/SRAM macrocells for L1 data caches

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Design, performance, and energy consumption of eDRAM/SRAM macrocells for L1 data caches

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dc.contributor.author Valero Bresó, Alejandro es_ES
dc.contributor.author Petit Martí, Salvador Vicente es_ES
dc.contributor.author Sahuquillo Borrás, Julio es_ES
dc.contributor.author López Rodríguez, Pedro Juan es_ES
dc.contributor.author Duato Marín, José Francisco es_ES
dc.date.accessioned 2014-04-01T06:23:50Z
dc.date.issued 2012-09
dc.identifier.issn 0018-9340
dc.identifier.uri http://hdl.handle.net/10251/36749
dc.description (c) 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works es_ES
dc.description.abstract SRAM and DRAM have been the predominant technologies used to implement memory cells in computer systems, each one having its advantages and shortcomings. SRAM cells are faster and require no refresh since reads are not destructive. In contrast, DRAM cells provide higher density and minimal leakage energy since there are no paths within the cell from Vdd to ground. Recently, DRAM cells have been embedded in logic-based technology (eDRAM), thus overcoming the speed limit of typical DRAM cells. In this paper, we propose a hybrid n-bit macrocell that implements one SRAM cell and n-1 eDRAM cells. This cell is aimed at being used in an n-way set-associative first-level data cache. Architectural mechanisms (e.g., special writeback policies) have been devised to completely avoid refresh logic. Performance, energy, and area have been analyzed in detail. Experimental results show that using typical eDRAM capacitors, and compared to a conventional cache, a 4-way set-associative hybrid cache reduces both energy consumption and area up to 54 and 29 percent, respectively, while having negligible impact on performance (less than 2 percent). es_ES
dc.description.sponsorship This work was supported by the Spanish Ministerio de Ciencia e Innovacion (MICINN), and jointly financed with Plan E funds under Grant TIN2009-14475-C04-01 and by Consolider-Ingenio 2010 under Grant CSD2006-00046. en_EN
dc.format.extent 12 es_ES
dc.language Inglés es_ES
dc.publisher Institute of Electrical and Electronics Engineers (IEEE) es_ES
dc.relation Spanish Ministerio de Ciencia e Innovacion (MICINN) es_ES
dc.relation Consolider-Ingenio [CSD2006-00046] es_ES
dc.relation Plan E funds [TIN2009-14475-C04-01] es_ES
dc.relation.ispartof IEEE Transactions on Computers es_ES
dc.rights Reserva de todos los derechos es_ES
dc.subject Retention time es_ES
dc.subject Static and dynamic energy es_ES
dc.subject Static and dynamic memory cells es_ES
dc.subject Way prediction es_ES
dc.subject.classification ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES es_ES
dc.title Design, performance, and energy consumption of eDRAM/SRAM macrocells for L1 data caches es_ES
dc.type Artículo es_ES
dc.embargo.lift 10000-01-01
dc.embargo.terms forever es_ES
dc.identifier.doi 10.1109/TC.2011.138
dc.rights.accessRights Abierto es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors es_ES
dc.description.bibliographicCitation Valero Bresó, A.; Petit Martí, SV.; Sahuquillo Borrás, J.; López Rodríguez, PJ.; Duato Marín, JF. (2012). Design, performance, and energy consumption of eDRAM/SRAM macrocells for L1 data caches. IEEE Transactions on Computers. 61(9):1231-1242. doi:10.1109/TC.2011.138 es_ES
dc.description.accrualMethod Senia es_ES
dc.relation.publisherversion http://dx.doi.org/10.1109/TC.2011.138 es_ES
dc.description.upvformatpinicio 1231 es_ES
dc.description.upvformatpfin 1242 es_ES
dc.type.version info:eu repo/semantics/publishedVersion es_ES
dc.description.volume 61 es_ES
dc.description.issue 9 es_ES
dc.relation.senia 234034


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