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On the impact of within-die process variation in GALS-Based NoC Performance

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On the impact of within-die process variation in GALS-Based NoC Performance

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Hernández Luz, C.; Roca Pérez, A.; Silla Jiménez, F.; Flich Cardo, J.; Duato Marín, JF. (2012). On the impact of within-die process variation in GALS-Based NoC Performance. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 31(2):294-307. doi:10.1109/TCAD.2011.2170071

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/37054

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Title: On the impact of within-die process variation in GALS-Based NoC Performance
Author:
UPV Unit: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Issued date:
Abstract:
[EN] Current integration scales allow designing chip multiprocessors (CMP), where cores are interconnected by means of a network-on-chip (NoC). Unfortunately, the small feature size of current integration scales causes ...[+]
Subjects: GALS , Networks-on-chip , Process variation
Copyrigths: Cerrado
Source:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. (issn: 0278-0070 )
DOI: 10.1109/TCAD.2011.2170071
Publisher:
Institute of Electrical and Electronics Engineers (IEEE)
Publisher version: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6132647
Project ID: info:eu-repo/grantAgreement/EC/FP7/248972
Thanks:
This work was supported in part by the Spanish MEC and MICINN, as well as European Commission FEDER funds, under Grants CSD2006-00046 and TIN2009-14475-C04, and in part by the project NaNoC (project label 248972), which ...[+]
Type: Artículo

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