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On the impact of within-die process variation in GALS-Based NoC Performance

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On the impact of within-die process variation in GALS-Based NoC Performance

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Hernández Luz, C.; Roca Pérez, A.; Silla Jiménez, F.; Flich Cardo, J.; Duato Marín, JF. (2012). On the impact of within-die process variation in GALS-Based NoC Performance. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 31(2):294-307. doi:10.1109/TCAD.2011.2170071

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Título: On the impact of within-die process variation in GALS-Based NoC Performance
Autor:
Entidad UPV: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Fecha difusión:
Resumen:
Current integration scales allow designing chip multiprocessors (CMP), where cores are interconnected by means of a network-on-chip (NoC). Unfortunately, the small feature size of current integration scales causes some ...[+]
Palabras clave: GALS , Networks-on-chip , Process variation
Derechos de uso: Cerrado
Fuente:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. (issn: 0278-0070 )
DOI: 10.1109/TCAD.2011.2170071
Editorial:
Institute of Electrical and Electronics Engineers (IEEE)
Versión del editor: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6132647
Código del Proyecto: info:eu-repo/grantAgreement/EC/FP7/248972
Agradecimientos:
Manuscript received June 17, 2011; revised July 29, 2011; accepted August 18, 2011. Date of current version January 20, 2012. This work was supported in part by the Spanish MEC and MICINN, as well as European Commission ...[+]
Tipo: Artículo

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