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On the impact of within-die process variation in GALS-Based NoC Performance

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On the impact of within-die process variation in GALS-Based NoC Performance

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dc.contributor.author Hernández Luz, Carles es_ES
dc.contributor.author Roca Pérez, Antoni es_ES
dc.contributor.author Silla Jiménez, Federico es_ES
dc.contributor.author Flich Cardo, José es_ES
dc.contributor.author Duato Marín, José Francisco es_ES
dc.date.accessioned 2014-04-17T07:56:28Z
dc.date.issued 2012-02
dc.identifier.issn 0278-0070
dc.identifier.uri http://hdl.handle.net/10251/37054
dc.description.abstract [EN] Current integration scales allow designing chip multiprocessors (CMP), where cores are interconnected by means of a network-on-chip (NoC). Unfortunately, the small feature size of current integration scales causes some unpredictability in manufactured devices because of process variation. In NoCs, variability may affect links and routers causing them not to match the parameters established at design time. In this paper, we first analyze the way that manufacturing deviations affect the components of a NoC by applying a new comprehensive and detailed within-die variability model to 200 instances of an 8¿8 mesh NoC synthesized using 45 nm technology. Later, we show that GALS-based NoCs present communication bottlenecks under process variation which cannot be avoided by using just device-level solutions but higher level architectural approaches are required. Therefore, to overcome this performance reduction, we draft a novel architectural approach, called performance domains, intended to reduce the negative impact of variability on application execution time. This mechanism is suitable when several applications are simultaneously running in the CMP chip. es_ES
dc.description.sponsorship This work was supported in part by the Spanish MEC and MICINN, as well as European Commission FEDER funds, under Grants CSD2006-00046 and TIN2009-14475-C04, and in part by the project NaNoC (project label 248972), which is funded by the European Commission within the Research Program FP7. This paper was recommended by Associate Editor L.-P. Carloni. en_EN
dc.format.extent 14 es_ES
dc.language Inglés es_ES
dc.publisher Institute of Electrical and Electronics Engineers (IEEE) es_ES
dc.relation.ispartof IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems es_ES
dc.rights Reserva de todos los derechos es_ES
dc.subject GALS es_ES
dc.subject Networks-on-chip es_ES
dc.subject Process variation es_ES
dc.subject.classification ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES es_ES
dc.title On the impact of within-die process variation in GALS-Based NoC Performance es_ES
dc.type Artículo es_ES
dc.embargo.lift 10000-01-01
dc.embargo.terms forever es_ES
dc.identifier.doi 10.1109/TCAD.2011.2170071
dc.relation.projectID info:eu-repo/grantAgreement/EC/FP7/248972/EU/Nanoscale Silicon-Aware Network-on-Chip Design Platform/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/MEC//CSD2006-00046/ES/Arquitecturas fiables y de altas prestaciones para centros de proceso de datos y servidores de Internet/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/MICINN//TIN2009-14475-C04-01/ES/Arquitecturas De Servidores, Aplicaciones Y Servicios/ es_ES
dc.rights.accessRights Cerrado es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors es_ES
dc.description.bibliographicCitation Hernández Luz, C.; Roca Pérez, A.; Silla Jiménez, F.; Flich Cardo, J.; Duato Marín, JF. (2012). On the impact of within-die process variation in GALS-Based NoC Performance. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 31(2):294-307. https://doi.org/10.1109/TCAD.2011.2170071 es_ES
dc.description.accrualMethod S es_ES
dc.relation.publisherversion http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6132647 es_ES
dc.description.upvformatpinicio 294 es_ES
dc.description.upvformatpfin 307 es_ES
dc.type.version info:eu-repo/semantics/publishedVersion es_ES
dc.description.volume 31 es_ES
dc.description.issue 2 es_ES
dc.relation.senia 207767
dc.contributor.funder European Commission
dc.contributor.funder Ministerio de Ciencia e Innovación
dc.contributor.funder Ministerio de Educación y Ciencia es_ES


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