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Architecture extensions for efficient managament of scratch-pad Memory

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Architecture extensions for efficient managament of scratch-pad Memory

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Busquets Mataix, JV.; Catalá, C.; Martí Campoy, A. (2011). Architecture extensions for efficient managament of scratch-pad Memory. En Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. Springer Verlag (Germany). (6951):43-52. https://doi.org/10.1007/978-3-642-24154-3_5

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Metadatos del ítem

Título: Architecture extensions for efficient managament of scratch-pad Memory
Autor: Busquets Mataix, José Vicente Catalá, Carlos Martí Campoy, Antonio
Entidad UPV: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Fecha difusión:
Resumen:
Nowadays, many embedded processors include in their architecture on-chip static memories, so called scratch-pad memories (SPM). Compared to cache, these memories do not require complex control logic, thus resulting in ...[+]
Palabras clave: Embedded processors , Memory architecture , Scratch-pad memory , Complex control logic , Load Code , Memory segments
Derechos de uso: Reserva de todos los derechos
Fuente:
Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. (issn: 0302-9743 )
DOI: 10.1007/978-3-642-24154-3_5
Editorial:
Springer Verlag (Germany)
Versión del editor: http://link.springer.com/chapter/10.1007/978-3-642-24154-3_5
Título del congreso: 21st International Workshop, PATMOS 2011
Lugar del congreso: Madrid, Spain
Fecha congreso: September 26-29, 2011
Serie: Lecture Notes in Computer Science;6951
Código del Proyecto:
info:eu-repo/grantAgreement/GVA//GV%2F2007%2F122/
Agradecimientos:
This research was sponsored by local Government “Generalitat Valenciana” under project GV07/ 2007/122.
Tipo: Capítulo de libro

References

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