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Architecture extensions for efficient managament of scratch-pad Memory

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Architecture extensions for efficient managament of scratch-pad Memory

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dc.contributor.author Busquets Mataix, José Vicente es_ES
dc.contributor.author Catalá, Carlos es_ES
dc.contributor.author Martí Campoy, Antonio es_ES
dc.date.accessioned 2014-06-04T12:35:09Z
dc.date.issued 2011
dc.identifier.issn 0302-9743
dc.identifier.uri http://hdl.handle.net/10251/37923
dc.description.abstract Nowadays, many embedded processors include in their architecture on-chip static memories, so called scratch-pad memories (SPM). Compared to cache, these memories do not require complex control logic, thus resulting in increased efficiency both in silicon area and energy consumption. Last years, many papers have proposed algorithms to allocate memory segments in SPM in order to enhance its usage. However, very few care about the SPM architecture itself, to make it more controllable, more power efficient and faster. This paper proposes architecture extensions to automatically load code into the SPM whilst it is fetched for execution to reduce the SPM updating delays, which motivates a very dynamic use of the SPM. We test our proposal in a derivation of the Simplescalar simulator, with typical embedded benchmarks. The results show improvements, on average, of 30.6% in energy saving and 7.6% in performance compared to a system with cache. © 2011 Springer-Verlag. es_ES
dc.description.sponsorship This research was sponsored by local Government “Generalitat Valenciana” under project GV07/ 2007/122. es_ES
dc.format.extent 10 es_ES
dc.language Inglés es_ES
dc.publisher Springer Verlag (Germany) es_ES
dc.relation.ispartof Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation es_ES
dc.relation.ispartofseries Lecture Notes in Computer Science;6951
dc.rights Reserva de todos los derechos es_ES
dc.subject Embedded processors es_ES
dc.subject Memory architecture es_ES
dc.subject Scratch-pad memory es_ES
dc.subject Complex control logic es_ES
dc.subject Load Code es_ES
dc.subject Memory segments es_ES
dc.subject.classification ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES es_ES
dc.subject.classification ORGANIZACION DE EMPRESAS es_ES
dc.title Architecture extensions for efficient managament of scratch-pad Memory es_ES
dc.type Capítulo de libro es_ES
dc.embargo.lift 10000-01-01
dc.embargo.terms forever es_ES
dc.identifier.doi 10.1007/978-3-642-24154-3_5
dc.relation.projectID info:eu-repo/grantAgreement/GVA//GV%2F2007%2F122/ es_ES
dc.rights.accessRights Abierto es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors es_ES
dc.description.bibliographicCitation Busquets Mataix, JV.; Catalá, C.; Martí Campoy, A. (2011). Architecture extensions for efficient managament of scratch-pad Memory. En Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. Springer Verlag (Germany). (6951):43-52. https://doi.org/10.1007/978-3-642-24154-3_5 es_ES
dc.description.accrualMethod S es_ES
dc.relation.conferencename 21st International Workshop, PATMOS 2011 es_ES
dc.relation.conferencedate September 26-29, 2011 es_ES
dc.relation.conferenceplace Madrid, Spain es_ES
dc.relation.publisherversion http://link.springer.com/chapter/10.1007/978-3-642-24154-3_5 es_ES
dc.description.upvformatpinicio 43 es_ES
dc.description.upvformatpfin 52 es_ES
dc.type.version info:eu-repo/semantics/publishedVersion es_ES
dc.description.issue 6951 es_ES
dc.relation.senia 200424
dc.contributor.funder Generalitat Valenciana es_ES
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