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Silicon-aware distributed switch architecture for on-chip networks

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Silicon-aware distributed switch architecture for on-chip networks

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Roca Pérez, A.; Hernández Luz, C.; Flich Cardo, J.; Silla Jiménez, F.; Duato Marín, JF. (2013). Silicon-aware distributed switch architecture for on-chip networks. Journal of Systems Architecture. 59(7):505-515. doi:10.1016/j.sysarc.2013.03.008

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Título: Silicon-aware distributed switch architecture for on-chip networks
Autor:
Entidad UPV: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Fecha difusión:
Resumen:
[EN] It is well-known that current Chip MultiProcessor (CMP) and high-end MultiProcessor System-on-Chip (MPSoC) designs are growing in their number of components. Networks-on-Chip (NoC) provide the required connectivity ...[+]
Palabras clave: Networ-on-Chip , Switch design , Link power consumption
Derechos de uso: Cerrado
Fuente:
Journal of Systems Architecture. (issn: 1383-7621 )
DOI: 10.1016/j.sysarc.2013.03.008
Editorial:
Elsevier
Versión del editor: http://dx.doi.org/10.1016/j.sysarc.2013.03.008
Código del Proyecto: info:eu-repo/grantAgreement/EC/FP7/248972/EU
Agradecimientos:
This work was supported by the Spanish MEC and MICINN, as well as by European Commission FEDER funds, under Grant CSD2006-00046. It was also partly supported by the project NaNoC (project label 248972) which is funded by ...[+]
Tipo: Artículo

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