Mostrar el registro sencillo del ítem
dc.contributor.author | Roca Pérez, Antoni![]() |
es_ES |
dc.contributor.author | Hernández Luz, Carles![]() |
es_ES |
dc.contributor.author | Flich Cardo, José![]() |
es_ES |
dc.contributor.author | Silla Jiménez, Federico![]() |
es_ES |
dc.contributor.author | Duato Marín, José Francisco![]() |
es_ES |
dc.date.accessioned | 2014-09-24T18:14:33Z | |
dc.date.issued | 2013-08 | |
dc.identifier.issn | 1383-7621 | |
dc.identifier.uri | http://hdl.handle.net/10251/40164 | |
dc.description.abstract | [EN] It is well-known that current Chip MultiProcessor (CMP) and high-end MultiProcessor System-on-Chip (MPSoC) designs are growing in their number of components. Networks-on-Chip (NoC) provide the required connectivity for such CMP and MPSoC designs at reasonable costs. As technology advances, links become the critical component in the NoC due to their long delay and power consumption, becoming unacceptable for long global interconnects. In this paper we present a new switch architecture that reduces the negative impact of links on the NoC. We call our proposal distributed switch. The distributed switch spreads the circuitry of the switch onto the links. Thus, packets are buffered, routed, and forwarded at the same time they are crossing the link. Distributing a modular switch onto the link improves the trade off between the power consumption and the operating frequency of the entire network. On the contrary, area resources are increased. Additionally, the distributed switch presents better fault tolerance and process variation behavior with respect to a non-distributed switch. | es_ES |
dc.description.sponsorship | This work was supported by the Spanish MEC and MICINN, as well as by European Commission FEDER funds, under Grant CSD2006-00046. It was also partly supported by the project NaNoC (project label 248972) which is funded by the European Commission within the Research Programme FP7. | en_EN |
dc.language | Inglés | es_ES |
dc.publisher | Elsevier | es_ES |
dc.relation.ispartof | Journal of Systems Architecture | es_ES |
dc.rights | Reserva de todos los derechos | es_ES |
dc.subject | Networ-on-Chip | es_ES |
dc.subject | Switch design | es_ES |
dc.subject | Link power consumption | es_ES |
dc.subject.classification | ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES | es_ES |
dc.title | Silicon-aware distributed switch architecture for on-chip networks | es_ES |
dc.type | Artículo | es_ES |
dc.embargo.lift | 10000-01-01 | |
dc.embargo.terms | forever | es_ES |
dc.identifier.doi | 10.1016/j.sysarc.2013.03.008 | |
dc.relation.projectID | info:eu-repo/grantAgreement/MEC//CSD2006-00046/ES/Arquitecturas fiables y de altas prestaciones para centros de proceso de datos y servidores de Internet/ | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/EC/FP7/248972/EU/Nanoscale Silicon-Aware Network-on-Chip Design Platform/ | |
dc.rights.accessRights | Cerrado | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors | es_ES |
dc.description.bibliographicCitation | Roca Pérez, A.; Hernández Luz, C.; Flich Cardo, J.; Silla Jiménez, F.; Duato Marín, JF. (2013). Silicon-aware distributed switch architecture for on-chip networks. Journal of Systems Architecture. 59(7):505-515. https://doi.org/10.1016/j.sysarc.2013.03.008 | es_ES |
dc.description.accrualMethod | S | es_ES |
dc.relation.publisherversion | http://dx.doi.org/10.1016/j.sysarc.2013.03.008 | es_ES |
dc.description.upvformatpinicio | 505 | es_ES |
dc.description.upvformatpfin | 515 | es_ES |
dc.type.version | info:eu-repo/semantics/publishedVersion | es_ES |
dc.description.volume | 59 | es_ES |
dc.description.issue | 7 | es_ES |
dc.relation.senia | 258481 | |
dc.contributor.funder | European Commission | |
dc.contributor.funder | Ministerio de Educación y Ciencia | es_ES |