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Architecture of Generalized Bit-Flipping Decodingfor High-Rate Non-binary LDPC Codes

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Architecture of Generalized Bit-Flipping Decodingfor High-Rate Non-binary LDPC Codes

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García Herrero, FM.; Canet Subiela, MJ.; Valls Coquillat, J. (2013). Architecture of Generalized Bit-Flipping Decodingfor High-Rate Non-binary LDPC Codes. Circuits, Systems, and Signal Processing. 32:727-741. doi:10.1007/s00034-012-9481-3

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/44209

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Title: Architecture of Generalized Bit-Flipping Decodingfor High-Rate Non-binary LDPC Codes
Author:
UPV Unit: Universitat Politècnica de València. Departamento de Ingeniería Electrónica - Departament d'Enginyeria Electrònica
Universitat Politècnica de València. Instituto Universitario de Telecomunicación y Aplicaciones Multimedia - Institut Universitari de Telecomunicacions i Aplicacions Multimèdia
Issued date:
Abstract:
A VLSI architecture for the generalized bit-flipping decoding algorithm for non-binary low-density parity-check codes is proposed in this paper. The tentative decoding steps of the algorithm have been modifed to avoid ...[+]
Subjects: Galois Field , Non-binary low-density parity-check (LDPC) codes , VLSI , Decoder
Copyrigths: Cerrado
Source:
Circuits, Systems, and Signal Processing. (issn: 0278-081X )
DOI: 10.1007/s00034-012-9481-3
Publisher:
Springer Verlag (Germany)
Publisher version: http://dx.doi.org/10.1007/s00034-012-9481-3
Thanks:
This research was supported by FEDER and the Spanish Ministerio de Ciencia e Innovacion, under Grant No. TEC2008-06787 and TEC2011-27916. F. Garcia-Herrero has developed his work in this project thanks to a VALi+d grant ...[+]
Type: Artículo

References

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