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Architecture of Generalized Bit-Flipping Decodingfor High-Rate Non-binary LDPC Codes

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Architecture of Generalized Bit-Flipping Decodingfor High-Rate Non-binary LDPC Codes

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dc.contributor.author García Herrero, Francisco Miguel es_ES
dc.contributor.author Canet Subiela, Mª José es_ES
dc.contributor.author Valls Coquillat, Javier es_ES
dc.date.accessioned 2014-11-14T16:31:26Z
dc.date.available 2014-11-14T16:31:26Z
dc.date.issued 2013-04
dc.identifier.issn 0278-081X
dc.identifier.uri http://hdl.handle.net/10251/44209
dc.description.abstract A VLSI architecture for the generalized bit-flipping decoding algorithm for non-binary low-density parity-check codes is proposed in this paper. The tentative decoding steps of the algorithm have been modifed to avoid computing and storing a matrix of dimension N ×2q , for a code (N,K) over GF(2q ), reducing its complexity with a minimal penalization of its performance, less than 0.05 dB compared with the original algorithm. The architecture was synthesized using a 90 nm standard cell library, for the (837, 723) non-binary code over GF(25), requiring 590220 xor gates and achieving a throughput of 89Mbps. Additionally, it was implemented in a Virtex- VI FPGA device with a cost of 4070 slices and a throughput of 44.6 Mbps. es_ES
dc.description.sponsorship This research was supported by FEDER and the Spanish Ministerio de Ciencia e Innovacion, under Grant No. TEC2008-06787 and TEC2011-27916. F. Garcia-Herrero has developed his work in this project thanks to a VALi+d grant sponsored by Generalitat Valenciana (Conselleria d'Educacio). Grant No. ACIF/2011/023 and a FPU grant sponsored by the Spanish Government Grant No. AP2010-5178. en_EN
dc.language Inglés es_ES
dc.publisher Springer Verlag (Germany) es_ES
dc.relation.ispartof Circuits, Systems, and Signal Processing es_ES
dc.rights Reserva de todos los derechos es_ES
dc.subject Galois Field es_ES
dc.subject Non-binary low-density parity-check (LDPC) codes es_ES
dc.subject VLSI es_ES
dc.subject Decoder es_ES
dc.subject.classification TECNOLOGIA ELECTRONICA es_ES
dc.title Architecture of Generalized Bit-Flipping Decodingfor High-Rate Non-binary LDPC Codes es_ES
dc.type Artículo es_ES
dc.identifier.doi 10.1007/s00034-012-9481-3
dc.relation.projectID info:eu-repo/grantAgreement/MICINN//TEC2008-06787/ES/ARQUITECTURAS DE FEC PARA SISTEMAS DE COMUNICACIONES DE MUY ALTA VELOCIDAD/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/GVA//ACIF%2F2011%2F023/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/MECD//AP2010-5178/ES/AP2010-5178/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/MINECO//TEC2011-27916/ES/ALGORITMOS Y ARQUITECTURAS DE FEC PARA FUTUROS SISTEMAS DE COMUNICACIONES/ es_ES
dc.rights.accessRights Cerrado es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Ingeniería Electrónica - Departament d'Enginyeria Electrònica es_ES
dc.contributor.affiliation Universitat Politècnica de València. Instituto Universitario de Telecomunicación y Aplicaciones Multimedia - Institut Universitari de Telecomunicacions i Aplicacions Multimèdia es_ES
dc.description.bibliographicCitation García Herrero, FM.; Canet Subiela, MJ.; Valls Coquillat, J. (2013). Architecture of Generalized Bit-Flipping Decodingfor High-Rate Non-binary LDPC Codes. Circuits, Systems, and Signal Processing. 32:727-741. https://doi.org/10.1007/s00034-012-9481-3 es_ES
dc.description.accrualMethod S es_ES
dc.relation.publisherversion http://dx.doi.org/10.1007/s00034-012-9481-3 es_ES
dc.description.upvformatpinicio 727 es_ES
dc.description.upvformatpfin 741 es_ES
dc.type.version info:eu-repo/semantics/publishedVersion es_ES
dc.description.volume 32 es_ES
dc.relation.senia 235530
dc.contributor.funder Ministerio de Ciencia e Innovación es_ES
dc.contributor.funder Ministerio de Educación, Cultura y Deporte es_ES
dc.contributor.funder Ministerio de Economía y Competitividad es_ES
dc.contributor.funder Generalitat Valenciana es_ES
dc.contributor.funder European Regional Development Fund es_ES
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