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LUT saving in embedded FPGAs for cache locking in real-time systems

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LUT saving in embedded FPGAs for cache locking in real-time systems

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Martí Campoy, A.; Rodríguez Ballester, F.; Ors Carot, R. (2013). LUT saving in embedded FPGAs for cache locking in real-time systems. International Journal On Advances in Systems and Measurements. 6(1-2):190-199. http://hdl.handle.net/10251/46758

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Title: LUT saving in embedded FPGAs for cache locking in real-time systems
Author: Martí Campoy, Antonio Rodríguez Ballester, Francisco Ors Carot, Rafael
UPV Unit: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Issued date:
Abstract:
[EN] In recent years, cache locking have appeared as a solution to ease the schedulability analysis of real-time systems using cache memories maintaining, at the same time, similar performance improvements than regular ...[+]
Subjects: Real time systems , Cache locking , FPGA , Memory hierarchy
Copyrigths: Reconocimiento - No comercial - Compartir igual (by-nc-sa)
Source:
International Journal On Advances in Systems and Measurements. (issn: 1942-261X )
Publisher version: http://www.iariajournals.org/systems_and_measurements/
Project ID:
UPV/PAID-06-11/2055
MICINN/TIN2011-28435- C03-01
Thanks:
This work has been partially supported by PAID-06-11/2055 of Universitat Politecnica de València and TIN2011-28435- C03-01 of Ministerio de Ciencia e Innovacion.
Type: Artículo

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