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Modifed Shuffled Based Architecture for High Throughput Decoding of LDPC Codes

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Modifed Shuffled Based Architecture for High Throughput Decoding of LDPC Codes

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Angarita, F.; Sansaloni Balaguer, TM.; Pérez Pascual, MA.; Valls Coquillat, J. (2012). Modifed Shuffled Based Architecture for High Throughput Decoding of LDPC Codes. Journal of Signal Processing Systems. 68(2):139-149. doi:10.1007/s11265-011-0592-z

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/47024

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Title: Modifed Shuffled Based Architecture for High Throughput Decoding of LDPC Codes
Author:
UPV Unit: Universitat Politècnica de València. Instituto Universitario de Telecomunicación y Aplicaciones Multimedia - Institut Universitari de Telecomunicacions i Aplicacions Multimèdia
Universitat Politècnica de València. Departamento de Ingeniería Electrónica - Departament d'Enginyeria Electrònica
Issued date:
Abstract:
Low Density Parity-Check (LDPC) codes achieve the best performance when they are decoded with the sum-product (SP) algorithm. This is a two-phase iterative algorithm where two types of messages are interchanged and updated ...[+]
Subjects: Low-density parity-check (LDPC) codes , Sum-Product algorithm , Shuffled scheme , VLSI , High-throughput
Copyrigths: Cerrado
Source:
Journal of Signal Processing Systems. (issn: 1939-8018 )
DOI: 10.1007/s11265-011-0592-z
Publisher:
Springer Verlag (Germany)
Publisher version: http://dx.doi.org/10.1007/s11265-011-0592-z
Thanks:
This research was supported by Fondo Europeo de Desarrollo Regional (FEDER), the Spanish Ministerio de Ciencia e Innovacion, under Grant No. TEC2008-06787.
Type: Artículo

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