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dc.contributor.author | Angarita, Fabián![]() |
es_ES |
dc.contributor.author | Sansaloni Balaguer, Trinidad Mª![]() |
es_ES |
dc.contributor.author | Pérez Pascual, Mª Asunción![]() |
es_ES |
dc.contributor.author | Valls Coquillat, Javier![]() |
es_ES |
dc.date.accessioned | 2015-02-13T11:45:55Z | |
dc.date.available | 2015-02-13T11:45:55Z | |
dc.date.issued | 2012-08 | |
dc.identifier.issn | 1939-8018 | |
dc.identifier.uri | http://hdl.handle.net/10251/47024 | |
dc.description.abstract | Low Density Parity-Check (LDPC) codes achieve the best performance when they are decoded with the sum-product (SP) algorithm. This is a two-phase iterative algorithm where two types of messages are interchanged and updated in each iteration. The group-shuffled or layered decoding schemes applied to the SP algorithm speed up its convergence by modifying its schedule, so they yield a reduction in the number of iterations required to achieve a given performance. However, the two-phase processing is still maintained. In this paper a modification of the group-shuffled scheme suitable for high-rate LDPC codes is proposed. The modification allows the overlapping of the two-phase computation, achieving a convergence speed up close to that of the group-shuffled scheme with higher throughput. Besides, high throughput architectures are presented for the modified algorithm. As an example, the proposed architecture has been implemented for the 2048-bit LDPC code of the IEEE 802.3an standard and it was synthesized in a 90 nm CMOS process achieving a throughput of 22.40 Gbps at 14 iterations with a clock frequency of 306 MHz and a total area of 10.5 mm(2). Furthermore, the decoder performs within 0.5 dB of the floating-point 100 iterations sum-product algorithm at a PER of 10(-5). | es_ES |
dc.description.sponsorship | This research was supported by Fondo Europeo de Desarrollo Regional (FEDER), the Spanish Ministerio de Ciencia e Innovacion, under Grant No. TEC2008-06787. | en_EN |
dc.language | Inglés | es_ES |
dc.publisher | Springer Verlag (Germany) | es_ES |
dc.relation.ispartof | Journal of Signal Processing Systems | es_ES |
dc.rights | Reserva de todos los derechos | es_ES |
dc.subject | Low-density parity-check (LDPC) codes | es_ES |
dc.subject | Sum-Product algorithm | es_ES |
dc.subject | Shuffled scheme | es_ES |
dc.subject | VLSI | es_ES |
dc.subject | High-throughput | es_ES |
dc.subject.classification | TECNOLOGIA ELECTRONICA | es_ES |
dc.title | Modifed Shuffled Based Architecture for High Throughput Decoding of LDPC Codes | es_ES |
dc.type | Artículo | es_ES |
dc.identifier.doi | 10.1007/s11265-011-0592-z | |
dc.relation.projectID | info:eu-repo/grantAgreement/MICINN//TEC2008-06787/ES/ARQUITECTURAS DE FEC PARA SISTEMAS DE COMUNICACIONES DE MUY ALTA VELOCIDAD/ | es_ES |
dc.rights.accessRights | Cerrado | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Instituto Universitario de Telecomunicación y Aplicaciones Multimedia - Institut Universitari de Telecomunicacions i Aplicacions Multimèdia | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Departamento de Ingeniería Electrónica - Departament d'Enginyeria Electrònica | es_ES |
dc.description.bibliographicCitation | Angarita, F.; Sansaloni Balaguer, TM.; Pérez Pascual, MA.; Valls Coquillat, J. (2012). Modifed Shuffled Based Architecture for High Throughput Decoding of LDPC Codes. Journal of Signal Processing Systems. 68(2):139-149. https://doi.org/10.1007/s11265-011-0592-z | es_ES |
dc.description.accrualMethod | S | es_ES |
dc.relation.publisherversion | http://dx.doi.org/10.1007/s11265-011-0592-z | es_ES |
dc.description.upvformatpinicio | 139 | es_ES |
dc.description.upvformatpfin | 149 | es_ES |
dc.type.version | info:eu-repo/semantics/publishedVersion | es_ES |
dc.description.volume | 68 | es_ES |
dc.description.issue | 2 | es_ES |
dc.relation.senia | 222690 | |
dc.contributor.funder | Ministerio de Ciencia e Innovación | es_ES |
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