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Efficient routing in heterogeneous SoC designs with small implementation overhead

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Efficient routing in heterogeneous SoC designs with small implementation overhead

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dc.contributor.author Cano Reyes, José es_ES
dc.contributor.author Flich Cardo, José es_ES
dc.contributor.author Roca Pérez, Antoni es_ES
dc.contributor.author Duato Marín, José Francisco es_ES
dc.contributor.author Coppola, Marcello es_ES
dc.contributor.author Locatelli, Riccardo es_ES
dc.date.accessioned 2015-06-01T09:52:16Z
dc.date.available 2015-06-01T09:52:16Z
dc.date.issued 2014-03
dc.identifier.issn 0018-9340
dc.identifier.uri http://hdl.handle.net/10251/51034
dc.description.abstract In application-specific SoCs, the irregularity of the topology ends up in a complex and customized implementation of the routing algorithm, usually relying on routing tables implemented with memory structures at source end nodes. As system size increases, the routing tables also increase in size with nonnegligible impact on power, area, and latency overheads. In this paper, we present a routing implementation for application-specific SoCs able to implement in an efficient manner (with no routing tables and using a small logic block in every switch) a deadlock-free routing algorithm in these irregular networks. The mechanism relies on a tool that maps the initial irregular topology of the SoC system into a logical regular structure where the mechanism can be applied. We provide details for both the mapping tool and the proposed routing mechanism. Evaluation results show the effectiveness of the mapping tool as well as the low area and timing requirements of the mechanism. With the mapping tool and the routing mechanism, complex irregular SoC topologies can now be supported without the need for routing tables. es_ES
dc.description.sponsorship This work was supported by the Spanish MEC and MICINN, as well as European Commission FEDER funds, under Grant CSD2006-00046. It was also partly supported by the COMCAS project (CA501), a project labeled within the framework of CATRENE, the EUREKA cluster for Application and Technology Research in Europe on NanoElectronics. en_EN
dc.language Inglés es_ES
dc.publisher Institute of Electrical and Electronics Engineers (IEEE) es_ES
dc.relation Spanish MEC es_ES
dc.relation Spanish MICINN es_ES
dc.relation European Commission FEDER funds [CSD2006-00046] es_ES
dc.relation COMCAS project [CA501] es_ES
dc.relation.ispartof IEEE Transactions on Computers es_ES
dc.rights Reserva de todos los derechos es_ES
dc.subject Systems-on-chip es_ES
dc.subject Networks-on-chip es_ES
dc.subject Routing es_ES
dc.subject Evaluation es_ES
dc.subject Network topology es_ES
dc.subject Algorithm design and analysis es_ES
dc.subject.classification ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES es_ES
dc.title Efficient routing in heterogeneous SoC designs with small implementation overhead es_ES
dc.type Artículo es_ES
dc.identifier.doi 10.1109/TC.2012.299
dc.rights.accessRights Abierto es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors es_ES
dc.description.bibliographicCitation Cano Reyes, J.; Flich Cardo, J.; Roca Pérez, A.; Duato Marín, JF.; Coppola, M.; Locatelli, R. (2014). Efficient routing in heterogeneous SoC designs with small implementation overhead. IEEE Transactions on Computers. 63(3):557-569. doi:10.1109/TC.2012.299 es_ES
dc.description.accrualMethod Senia es_ES
dc.relation.publisherversion http://dx.doi.org/10.1109/TC.2012.299 es_ES
dc.description.upvformatpinicio 557 es_ES
dc.description.upvformatpfin 569 es_ES
dc.type.version info:eu-repo/semantics/publishedVersion es_ES
dc.description.volume 63 es_ES
dc.description.issue 3 es_ES
dc.relation.senia 289680


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