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dc.contributor.author | Angarita, Fabián | es_ES |
dc.contributor.author | Valls Coquillat, Javier | es_ES |
dc.contributor.author | Almenar Terré, Vicenç | es_ES |
dc.contributor.author | Torres Carot, Vicente | es_ES |
dc.date.accessioned | 2015-06-29T15:28:42Z | |
dc.date.available | 2015-06-29T15:28:42Z | |
dc.date.issued | 2014-07 | |
dc.identifier.issn | 1549-8328 | |
dc.identifier.uri | http://hdl.handle.net/10251/52443 | |
dc.description.abstract | This paper proposes a low-complexity min-sum algorithm for decoding low-density parity-check codes. It is an improved version of the single-minimum algorithm where the two-minimum calculation is replaced by one minimum calculation and a second minimum emulation. In the proposed one, variable correction factors that depend on the iteration number are introduced and the second minimum emulation is simplified, reducing by this way the decoder complexity. This proposal improves the performance of the single-minimum algorithm, approaching to the normalized min-sum performance in the water-fall region. Also, the error-floor region is analyzed for the code of the IEEE 802.3an standard showing that the trapping sets are decoded due to a slow down of the convergence of the algorithm. An error-floor free operation below BER = 10(-15) is shown for this code by means of a field-programmable gate array (FPGA)-based hardware emulator. A layered decoder is implemented in a 90-nm CMOS technology achieving 12.8 Gbps with an area of 3.84 mm(2) | es_ES |
dc.description.sponsorship | This work was supported by the Spanish Ministerio de Economia y Competitividad under Grants TEC2011-27916 and TEC2012-38558-C02-02. This paper was recommended by Associate Editor J. Ma. | en_EN |
dc.language | Inglés | es_ES |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | es_ES |
dc.relation.ispartof | IEEE Transactions on Circuits and Systems I: Regular Papers | es_ES |
dc.rights | Reserva de todos los derechos | es_ES |
dc.subject | Error correction codes (ECC) | es_ES |
dc.subject | Error-floor | es_ES |
dc.subject | Lowdensity parity-check (LDPC) codes | es_ES |
dc.subject | VLSI | es_ES |
dc.subject.classification | TEORIA DE LA SEÑAL Y COMUNICACIONES | es_ES |
dc.subject.classification | TECNOLOGIA ELECTRONICA | es_ES |
dc.title | Reduced-complexity min-sum algorithm for decoding LDPC codes with low error-floor | es_ES |
dc.type | Artículo | es_ES |
dc.identifier.doi | 10.1109/TCSI.2014.2304660 | |
dc.relation.projectID | info:eu-repo/grantAgreement/MICINN//TEC2011-27916/ES/ALGORITMOS Y ARQUITECTURAS DE FEC PARA FUTUROS SISTEMAS DE COMUNICACIONES/ | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/MINECO//TEC2012-38558-C02-02/ES/PROCESADO DIGITAL DE SEÑALES ÓPTICAS EN MEDIOS GUIADOS/ | es_ES |
dc.rights.accessRights | Cerrado | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Instituto Universitario de Telecomunicación y Aplicaciones Multimedia - Institut Universitari de Telecomunicacions i Aplicacions Multimèdia | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Departamento de Ingeniería Electrónica - Departament d'Enginyeria Electrònica | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Departamento de Comunicaciones - Departament de Comunicacions | es_ES |
dc.description.bibliographicCitation | Angarita, F.; Valls Coquillat, J.; Almenar Terré, V.; Torres Carot, V. (2014). Reduced-complexity min-sum algorithm for decoding LDPC codes with low error-floor. IEEE Transactions on Circuits and Systems I: Regular Papers. 61(7):2150-2158. https://doi.org/10.1109/TCSI.2014.2304660 | es_ES |
dc.description.accrualMethod | S | es_ES |
dc.relation.publisherversion | http://dx.doi.org/10.1109/TCSI.2014.2304660 | es_ES |
dc.description.upvformatpinicio | 2150 | es_ES |
dc.description.upvformatpfin | 2158 | es_ES |
dc.type.version | info:eu-repo/semantics/publishedVersion | es_ES |
dc.description.volume | 61 | es_ES |
dc.description.issue | 7 | es_ES |
dc.relation.senia | 283758 | |
dc.contributor.funder | Ministerio de Ciencia e Innovación | es_ES |
dc.contributor.funder | Ministerio de Economía y Competitividad | es_ES |