Resumen:
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[EN] In this project, different router architectures will be designed, together with different connection patterns among routers, which will lead to different topologies. The goal is the exploration of resource overheads ...[+]
[EN] In this project, different router architectures will be designed, together with different connection patterns among routers, which will lead to different topologies. The goal is the exploration of resource overheads and performance achieved in an FPGA-based environment with a completed multicore system developed. The work will analyze which is the best router design and topology when focusing on the relative performance achieved per cost unit.
In addition, new router techniques will be explored in order to reduce the latency of the network, thus improving performance.
The project will set a baseline configuration which is made of a 2D mesh topology with XY routing. The project will address topologies like concentrated mesh, torus network, mesh with express channels, and flattened butterfly.
The work will be developed completely on an FPGA-based environment with models deployed in Verilog, being synthesized and implemented on the FPGA board.
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[ES] In this project, different router architectures will be designed, together with different connection patterns among routers, which will lead to different topologies. The goal is the exploration of resource overheads ...[+]
[ES] In this project, different router architectures will be designed, together with different connection patterns among routers, which will lead to different topologies. The goal is the exploration of resource overheads and performance achieved in an FPGA-based environment with a completed multicore system developed. The work will analyze which is the best router design and topology when focusing on the relative performance achieved per cost unit.
In addition, new router techniques will be explored in order to reduce the latency of the network, thus improving performance.
The project will set a baseline configuration which is made of a 2D mesh topology with XY routing. The project will address topologies like concentrated mesh, torus network, mesh with express channels, and flattened butterfly.
The work will be developed completely on an FPGA-based environment with models deployed in Verilog, being synthesized and implemented on the FPGA board.
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