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Design, implementation, and analysis of router architectures and network topologies for FPGA-Based Multicore System

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Design, implementation, and analysis of router architectures and network topologies for FPGA-Based Multicore System

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dc.contributor.advisor Flich Cardo, José es_ES
dc.contributor.author Juvaa, Boldbaatar es_ES
dc.date.accessioned 2015-09-29T09:57:50Z
dc.date.available 2015-09-29T09:57:50Z
dc.date.created 2015-09-11
dc.date.issued 2015-09-29 es_ES
dc.identifier.uri http://hdl.handle.net/10251/55240
dc.description.abstract [EN] In this project, different router architectures will be designed, together with different connection patterns among routers, which will lead to different topologies. The goal is the exploration of resource overheads and performance achieved in an FPGA-based environment with a completed multicore system developed. The work will analyze which is the best router design and topology when focusing on the relative performance achieved per cost unit. In addition, new router techniques will be explored in order to reduce the latency of the network, thus improving performance. The project will set a baseline configuration which is made of a 2D mesh topology with XY routing. The project will address topologies like concentrated mesh, torus network, mesh with express channels, and flattened butterfly. The work will be developed completely on an FPGA-based environment with models deployed in Verilog, being synthesized and implemented on the FPGA board. es_ES
dc.description.abstract [ES] In this project, different router architectures will be designed, together with different connection patterns among routers, which will lead to different topologies. The goal is the exploration of resource overheads and performance achieved in an FPGA-based environment with a completed multicore system developed. The work will analyze which is the best router design and topology when focusing on the relative performance achieved per cost unit. In addition, new router techniques will be explored in order to reduce the latency of the network, thus improving performance. The project will set a baseline configuration which is made of a 2D mesh topology with XY routing. The project will address topologies like concentrated mesh, torus network, mesh with express channels, and flattened butterfly. The work will be developed completely on an FPGA-based environment with models deployed in Verilog, being synthesized and implemented on the FPGA board. es_ES
dc.language Inglés es_ES
dc.publisher Universitat Politècnica de València es_ES
dc.rights Reserva de todos los derechos es_ES
dc.subject Networks-on-chip es_ES
dc.subject FPGA es_ES
dc.subject Routing algorithms es_ES
dc.subject Topologies es_ES
dc.subject.classification ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES es_ES
dc.subject.other Máster Universitario en Ingeniería de Computadores y Redes-Màster Universitari en Enginyeria de Computadors i Xarxes es_ES
dc.title Design, implementation, and analysis of router architectures and network topologies for FPGA-Based Multicore System es_ES
dc.type Tesis de máster es_ES
dc.rights.accessRights Abierto es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors es_ES
dc.description.bibliographicCitation Juvaa, B. (2015). Design, implementation, and analysis of router architectures and network topologies for FPGA-Based Multicore System. http://hdl.handle.net/10251/55240 es_ES
dc.description.accrualMethod TFGM es_ES
dc.relation.pasarela TFGM\19218 es_ES


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