Valero Bresó, A.; Petit Martí, SV.; Sahuquillo Borrás, J.; Kaeli, DR.; Duato Marín, JF. (2015). A reuse-based refresh policy for energy-aware eDRAM caches. Microprocessors and Microsystems. 39(1):37-48. doi:10.1016/j.micpro.2014.12.001
Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/64110
Title:
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A reuse-based refresh policy for energy-aware eDRAM caches
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Author:
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Valero Bresó, Alejandro
Petit Martí, Salvador Vicente
Sahuquillo Borrás, Julio
Kaeli, David R.
Duato Marín, José Francisco
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UPV Unit:
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Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
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Issued date:
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Abstract:
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DRAM technology requires refresh operations to be performed in order to avoid data loss due to capacitance
leakage. Refresh operations consume a significant amount of dynamic energy, which increases
with the storage ...[+]
DRAM technology requires refresh operations to be performed in order to avoid data loss due to capacitance
leakage. Refresh operations consume a significant amount of dynamic energy, which increases
with the storage capacity. To reduce this amount of energy, prior work has focused on reducing refreshes
in off-chip memories. However, this problem also appears in on-chip eDRAM memories implemented in
current low-level caches. The refresh energy can dominate the dynamic consumption when a high percentage
of the chip area is devoted to eDRAM cache structures.
Replacement algorithms for high-associativity low-level caches select the victim block avoiding blocks
more likely to be reused soon. This paper combines the state-of-the-art MRUT replacement algorithm
with a novel refresh policy. Refresh operations are performed based on information produced by the
replacement algorithm. The proposed refresh policy is implemented on top of an energy-aware eDRAM
cache architecture, which implements bank-prediction and swap operations to save energy.
Experimental results show that, compared to a conventional eDRAM design, the proposed energyaware
cache can achieve by 72% refresh energy savings. Considering the entire on-chip memory hierarchy
consumption, the overall energy savings are 30%. These benefits come with minimal impact on performance
(by 1.2%) and area overhead (by 0.4%).
2014 Elsevier B.V. All rights reserved.
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Subjects:
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On-chip caches
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Reuse information
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Selective refresh
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Copyrigths:
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Reserva de todos los derechos
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Source:
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Microprocessors and Microsystems. (issn:
0141-9331
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DOI:
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10.1016/j.micpro.2014.12.001
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Publisher:
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Elsevier
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Publisher version:
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http://dx.doi.org/10.1016/j.micpro.2014.12.001
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Project ID:
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Spanish Ministerio de Economia y Competitiyidad (MINECO)/ FEDER/ TIN2012-38341-C04-01
Intel Early Career Honor Programme Award
Intel Doctoral Student Honor Programme Award
NSF/ CNS-1319501
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Thanks:
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This work was supported by the Spanish Ministerio de Economia y Competitiyidad (MINECO) and FEDER funds under Grant TIN2012-38341-C04-01. Additionally, it was also supported by the Intel Early Career Honor Programme Award ...[+]
This work was supported by the Spanish Ministerio de Economia y Competitiyidad (MINECO) and FEDER funds under Grant TIN2012-38341-C04-01. Additionally, it was also supported by the Intel Early Career Honor Programme Award and the Intel Doctoral Student Honor Programme Award. Prof. David R. Kaeli was supported in part by an NSF Award, CNS-1319501.
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Type:
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Artículo
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