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Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

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Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

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Roca Pérez, A.; Hernández Luz, C.; Lodde, M.; Flich Cardo, J. (2015). Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems. Computers and Electrical Engineering. 45:374-385. doi:10.1016/j.compeleceng.2015.04.020

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/64645

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Title: Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems
Author:
UPV Unit: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Issued date:
Abstract:
Manycore CMP systems are expected to grow to tens or even hundreds of cores. In this paper we show that the effective co-design of both, the network-on-chip and the coherence protocol, improves performance and power meanwhile ...[+]
Subjects: Chip multiprocessor , Network-on-chip , Network architecture , Coherence protocol
Copyrigths: Reserva de todos los derechos
Source:
Computers and Electrical Engineering. (issn: 0045-7906 )
DOI: 10.1016/j.compeleceng.2015.04.020
Publisher:
Elsevier
Publisher version: http://dx.doi.org/10.1016/j.compeleceng.2015.04.020
Type: Artículo

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