- -

Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

RiuNet: Institutional repository of the Polithecnic University of Valencia

Share/Send to

Cited by

Statistics

Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

Show simple item record

Files in this item

dc.contributor.author Roca Pérez, Antoni es_ES
dc.contributor.author Hernández Luz, Carles es_ES
dc.contributor.author Lodde, Mario es_ES
dc.contributor.author Flich Cardo, José es_ES
dc.date.accessioned 2016-05-24T09:34:31Z
dc.date.available 2016-05-24T09:34:31Z
dc.date.issued 2015-07
dc.identifier.issn 0045-7906
dc.identifier.uri http://hdl.handle.net/10251/64645
dc.description.abstract Manycore CMP systems are expected to grow to tens or even hundreds of cores. In this paper we show that the effective co-design of both, the network-on-chip and the coherence protocol, improves performance and power meanwhile total area resources remain bounded. We propose a snoopy-aware network-on-chip topology made of two mesh-of-tree topologies. Reducing the complexity of the coherence protocol - and hence its resources - and moving this complexity to the network, leads to a global decrease in power consumption meanwhile area is barely affected. Benefits of our proposal are due to the high-throughput and low delay of the network, but also due to the simplicity of the coherence protocol. The proposed network and protocol minimizes communication amongst cores when compared to traditional solutions based either on 2D-mesh topologies or in directory-based protocols. (C) 2015 Elsevier Ltd. All rights reserved. es_ES
dc.language Inglés es_ES
dc.publisher Elsevier es_ES
dc.relation.ispartof Computers and Electrical Engineering es_ES
dc.rights Reserva de todos los derechos es_ES
dc.subject Chip multiprocessor es_ES
dc.subject Network-on-chip es_ES
dc.subject Network architecture es_ES
dc.subject Coherence protocol es_ES
dc.subject.classification ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES es_ES
dc.title Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems es_ES
dc.type Artículo es_ES
dc.identifier.doi 10.1016/j.compeleceng.2015.04.020
dc.rights.accessRights Abierto es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors es_ES
dc.description.bibliographicCitation Roca Pérez, A.; Hernández Luz, C.; Lodde, M.; Flich Cardo, J. (2015). Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems. Computers and Electrical Engineering. 45:374-385. doi:10.1016/j.compeleceng.2015.04.020 es_ES
dc.description.accrualMethod Senia es_ES
dc.relation.publisherversion http://dx.doi.org/10.1016/j.compeleceng.2015.04.020 es_ES
dc.description.upvformatpinicio 374 es_ES
dc.description.upvformatpfin 385 es_ES
dc.type.version info:eu-repo/semantics/publishedVersion es_ES
dc.description.volume 45 es_ES
dc.relation.senia 312122 es_ES


This item appears in the following Collection(s)

Show simple item record