Lacruz, JO.; García Herrero, FM.; Valls Coquillat, J.; Declercq, D. (2015). One minimum only trellis decoder for non-binary low-density parity-check codes. IEEE Transactions on Circuits and Systems I: Regular Papers. 62(1):177-184. https://doi.org/10.1109/TCSI.2014.2354753
Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/64714
Título:
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One minimum only trellis decoder for non-binary low-density parity-check codes
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Autor:
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Lacruz, Jesús Omar
García Herrero, Francisco Miguel
Valls Coquillat, Javier
Declercq, David
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Entidad UPV:
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Universitat Politècnica de València. Departamento de Ingeniería Electrónica - Departament d'Enginyeria Electrònica
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Fecha difusión:
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Resumen:
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A one minimum only decoder for Trellis-EMS (OMO T-EMS) and for Trellis-Min-max (OMO T-MM) is proposed in this paper. In this novel approach, we avoid computing the second minimum in messages of the check node processor, ...[+]
A one minimum only decoder for Trellis-EMS (OMO T-EMS) and for Trellis-Min-max (OMO T-MM) is proposed in this paper. In this novel approach, we avoid computing the second minimum in messages of the check node processor, and propose efficient estimators to infer the second minimum value. By doing so, we greatly reduce the complexity and at the same time improve latency and throughput of the derived architectures compared to the existing implementations of EMS and Min-max decoders. This solution has been applied to various NB-LDPC codes constructed over different Galois fields and with different degree distributions showing in all cases negligible performance loss compared to the ideal EMS and Min-max algorithms. In addition, two complete decoders for OMO T-EMS and OMO T-MM were implemented for the (837,726) NB-LDPC code over GF(32) for comparison proposals. A 90 nm CMOS process was applied, achieving a throughput of 711 Mbps and 818 Mbps respectively at a clock frequency of 250 MHz, with an area of 19.02 ${rm mm}^{2}$ and 16.10 ${rm mm}^{2}$ after place and route. To the best knowledge of the authors, the proposed decoders have higher throughput and area-time efficiency than any other solution for high-rate NB-LDPC codes with high Galois field order.
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Palabras clave:
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Check node processing
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Low-latency
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NB-LDPC
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OMO T-EMS
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OMO T-MM
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VLSI design
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Derechos de uso:
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Reserva de todos los derechos
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Fuente:
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IEEE Transactions on Circuits and Systems I: Regular Papers. (issn:
1549-8328
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DOI:
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10.1109/TCSI.2014.2354753
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Editorial:
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Institute of Electrical and Electronics Engineers (IEEE)
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Versión del editor:
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http://dx.doi.org/10.1109/TCSI.2014.2354753
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Código del Proyecto:
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info:eu-repo/grantAgreement/MICINN//TEC2011-27916/ES/ALGORITMOS Y ARQUITECTURAS DE FEC PARA FUTUROS SISTEMAS DE COMUNICACIONES/
info:eu-repo/grantAgreement/UPV//PAID-06-12-SP20120625/
info:eu-repo/grantAgreement/ME//AP2010-5178/ES/AP2010-5178/
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Descripción:
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© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
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Agradecimientos:
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This work was supported in part by the Spanish Ministerio de Ciencia e Innovacion under Grant TEC2011-27916 and in part by the Universitat Politecnica de Valencia under Grant PAID-06-2012-SP20120625. The work of F. ...[+]
This work was supported in part by the Spanish Ministerio de Ciencia e Innovacion under Grant TEC2011-27916 and in part by the Universitat Politecnica de Valencia under Grant PAID-06-2012-SP20120625. The work of F. Garcia-Herrero was supported by the Spanish Ministerio de Educacion under Grant AP2010-5178. David Declercq has been funded by the Institut Universitaire de France for this project. This paper was recommended by Associate Editor Z. Zhang.
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Tipo:
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Artículo
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