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One minimum only trellis decoder for non-binary low-density parity-check codes

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One minimum only trellis decoder for non-binary low-density parity-check codes

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dc.contributor.author Lacruz, Jesús Omar es_ES
dc.contributor.author García Herrero, Francisco Miguel es_ES
dc.contributor.author Valls Coquillat, Javier es_ES
dc.contributor.author Declercq, David es_ES
dc.date.accessioned 2016-05-25T15:26:20Z
dc.date.available 2016-05-25T15:26:20Z
dc.date.issued 2015-01
dc.identifier.issn 1549-8328
dc.identifier.uri http://hdl.handle.net/10251/64714
dc.description © 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. es_ES
dc.description.abstract A one minimum only decoder for Trellis-EMS (OMO T-EMS) and for Trellis-Min-max (OMO T-MM) is proposed in this paper. In this novel approach, we avoid computing the second minimum in messages of the check node processor, and propose efficient estimators to infer the second minimum value. By doing so, we greatly reduce the complexity and at the same time improve latency and throughput of the derived architectures compared to the existing implementations of EMS and Min-max decoders. This solution has been applied to various NB-LDPC codes constructed over different Galois fields and with different degree distributions showing in all cases negligible performance loss compared to the ideal EMS and Min-max algorithms. In addition, two complete decoders for OMO T-EMS and OMO T-MM were implemented for the (837,726) NB-LDPC code over GF(32) for comparison proposals. A 90 nm CMOS process was applied, achieving a throughput of 711 Mbps and 818 Mbps respectively at a clock frequency of 250 MHz, with an area of 19.02 ${rm mm}^{2}$ and 16.10 ${rm mm}^{2}$ after place and route. To the best knowledge of the authors, the proposed decoders have higher throughput and area-time efficiency than any other solution for high-rate NB-LDPC codes with high Galois field order. es_ES
dc.description.sponsorship This work was supported in part by the Spanish Ministerio de Ciencia e Innovacion under Grant TEC2011-27916 and in part by the Universitat Politecnica de Valencia under Grant PAID-06-2012-SP20120625. The work of F. Garcia-Herrero was supported by the Spanish Ministerio de Educacion under Grant AP2010-5178. David Declercq has been funded by the Institut Universitaire de France for this project. This paper was recommended by Associate Editor Z. Zhang. en_EN
dc.language Inglés es_ES
dc.publisher Institute of Electrical and Electronics Engineers (IEEE) es_ES
dc.relation.ispartof IEEE Transactions on Circuits and Systems I: Regular Papers es_ES
dc.rights Reserva de todos los derechos es_ES
dc.subject Check node processing es_ES
dc.subject Low-latency es_ES
dc.subject NB-LDPC es_ES
dc.subject OMO T-EMS es_ES
dc.subject OMO T-MM es_ES
dc.subject VLSI design es_ES
dc.subject.classification TECNOLOGIA ELECTRONICA es_ES
dc.title One minimum only trellis decoder for non-binary low-density parity-check codes es_ES
dc.type Artículo es_ES
dc.identifier.doi 10.1109/TCSI.2014.2354753
dc.relation.projectID info:eu-repo/grantAgreement/MICINN//TEC2011-27916/ES/ALGORITMOS Y ARQUITECTURAS DE FEC PARA FUTUROS SISTEMAS DE COMUNICACIONES/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/UPV//PAID-06-12-SP20120625/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/ME//AP2010-5178/ES/AP2010-5178/ es_ES
dc.rights.accessRights Abierto es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Ingeniería Electrónica - Departament d'Enginyeria Electrònica es_ES
dc.description.bibliographicCitation Lacruz, JO.; García Herrero, FM.; Valls Coquillat, J.; Declercq, D. (2015). One minimum only trellis decoder for non-binary low-density parity-check codes. IEEE Transactions on Circuits and Systems I: Regular Papers. 62(1):177-184. https://doi.org/10.1109/TCSI.2014.2354753 es_ES
dc.description.accrualMethod S es_ES
dc.relation.publisherversion http://dx.doi.org/10.1109/TCSI.2014.2354753 es_ES
dc.description.upvformatpinicio 177 es_ES
dc.description.upvformatpfin 184 es_ES
dc.type.version info:eu-repo/semantics/publishedVersion es_ES
dc.description.volume 62 es_ES
dc.description.issue 1 es_ES
dc.relation.senia 276935 es_ES
dc.contributor.funder Ministerio de Ciencia e Innovación es_ES
dc.contributor.funder Universitat Politècnica de València es_ES
dc.contributor.funder Ministerio de Educación es_ES
dc.contributor.funder Institut Universitaire de France es_ES


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