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Analysis and RTL Correlation of Instruction Set Simulators for Automotive Microcontroller Robustness Verification

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Analysis and RTL Correlation of Instruction Set Simulators for Automotive Microcontroller Robustness Verification

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dc.contributor.author Espinosa García, Jaime es_ES
dc.contributor.author Hernández Luz, Carles es_ES
dc.contributor.author Abella, Jaume es_ES
dc.contributor.author Andrés Martínez, David de es_ES
dc.contributor.author Ruiz García, Juan Carlos
dc.date.accessioned 2016-06-09T10:33:21Z
dc.date.available 2016-06-09T10:33:21Z
dc.date.issued 2015-06
dc.identifier.isbn 978-1-4503-3520-1
dc.identifier.uri http://hdl.handle.net/10251/65584
dc.description © ACM 2015 This is the author's version of the work. It is posted here for your personal use. Not for redistribution. The definitive Version of Record was published in ACM, In Proceedings of the 52nd Annual Design Automation Conference (p. 40). http://dx.doi.org/10.1145/2744769.2744798. es_ES
dc.description.abstract Increasingly complex microcontroller designs for safety-relevant automotive systems require the adoption of new methods and tools to enable a cost-effective verification of their robustness. In particular, costs associated to the certification against the IS026262 safety standard must be kept low for economical reasons. In this context, simulation-based verification using instruction set simulators (ISS) arises as a promising approach to partially cope with the increasing cost of the verification process as it allows taking design decisions in early design stages when modifications can be performed quickly and with low cost. However, it remains to be proven that verification in those stages provides accurate enough information to be used in the context of automotive microcontrollers. In this paper we analyze the existing correlation between fault injection experiments in an RTL microcontroller description and the information available at the ISS to enable accurate ISS-based fault injection. es_ES
dc.description.sponsorship The research leading to these results has received funding from the ARTEMIS Joint Undertaking VeTeSS project under grant agreement number 295311. This work has also been funded by the Ministry of Science and Technology of Spain under contract TIN2012-34557 and HiPEAC. Jaume Abella is partially supported by the Ministry of Economy and Competitiveness under Ramon y Cajal postdoctoral fellowship number RYC-2013-14717. es_ES
dc.format.extent 6 es_ES
dc.language Inglés es_ES
dc.publisher ACM es_ES
dc.relation MICINN/TIN2012-34557 es_ES
dc.relation info:eu-repo/grantAgreement/MINECO//RYC-2013-14717/ES/RYC-2013-14717/ es_ES
dc.rights Reserva de todos los derechos es_ES
dc.subject.classification INGENIERIA DE SISTEMAS Y AUTOMATICA es_ES
dc.subject.classification ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES es_ES
dc.title Analysis and RTL Correlation of Instruction Set Simulators for Automotive Microcontroller Robustness Verification es_ES
dc.type Comunicación en congreso es_ES
dc.identifier.doi 10.1145/2744769.2744798
dc.relation.projectID info:eu-repo/grantAgreement/EC/FP7/295311/EU/Verification and Testing to Support Functional Safety Standards/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/EC/H2020/871174/EU/High Performance Embedded Architecture and Compilation/ es_ES
dc.rights.accessRights Abierto es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Ingeniería de Sistemas y Automática - Departament d'Enginyeria de Sistemes i Automàtica es_ES
dc.description.bibliographicCitation Espinosa García, J.; Hernández Luz, C.; Abella, J.; Andrés Martínez, DD.; Ruiz García, JC. (2015). Analysis and RTL Correlation of Instruction Set Simulators for Automotive Microcontroller Robustness Verification. ACM. https://doi.org/10.1145/2744769.2744798 es_ES
dc.description.accrualMethod S es_ES
dc.relation.conferencename 52nd Design Automation Conference (DAC 2015) es_ES
dc.relation.conferencedate June, 7-11, 2015 es_ES
dc.relation.conferenceplace San Francisco, USA es_ES
dc.relation.publisherversion http://dl.acm.org/citation.cfm?doid=2744769.2744798 es_ES
dc.type.version info:eu-repo/semantics/publishedVersion es_ES
dc.relation.senia 299128 es_ES
dc.contributor.funder European Commission es_ES
dc.contributor.funder Ministerio de Ciencia e Innovación es_ES
dc.contributor.funder European Network on High-performance Embedded Architecture and Compilation es_ES
dc.contributor.funder Ministerio de Economía y Competitividad es_ES
dc.relation.references ARTEMIS Joint Undertaking.VeTeSS project:www.vetess.eu. es_ES
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