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dc.contributor.author | Espinosa García, Jaime | es_ES |
dc.contributor.author | Andrés Martínez, David de | es_ES |
dc.contributor.author | Gil, Pedro | es_ES |
dc.date.accessioned | 2016-06-09T12:06:06Z | |
dc.date.available | 2016-06-09T12:06:06Z | |
dc.date.issued | 2015-09 | |
dc.identifier.uri | http://hdl.handle.net/10251/65596 | |
dc.description.abstract | Technology advances provide a myriad of advantages for VLSI systems, but also increase the sensitivity of the combinational logic to different fault profiles. Shorter and shorter faults which up to date had been filtered, named as fugacious faults, require new attention as they are considered a feasible sign of warning prior to potential failures. Despite their increasing impact on modern VLSI systems, such faults are not largely considered today by the safety industry. Their early detection is however critical to enable an early evaluation of potential risks for the system and the subsequent deployment of suitable failure avoidance mechanisms. For instance, the early detection of fugacious faults will provide the necessary means to extend the mission time of a system thanks to the temporal avoidance of aging effects. Because classical detection mechanisms are not suited to cope with such fugacious faults, this paper proposes a method specifically designed to detect and diagnose them. Reported experiments will show the feasibility and interest of the proposal. | es_ES |
dc.description.sponsorship | This work has been funded by the Spanish Ministry of Economy ARENES project (TIN2012-38308-C02—01). | es_ES |
dc.format.extent | 8 | es_ES |
dc.language | Inglés | es_ES |
dc.publisher | IEEE Computer Society - Conference Publishing Services (CPS) | es_ES |
dc.rights | Reserva de todos los derechos | es_ES |
dc.subject | Fugacious faults | es_ES |
dc.subject | Fault detection | es_ES |
dc.subject | Fault diagnosis | es_ES |
dc.subject.classification | INGENIERIA DE SISTEMAS Y AUTOMATICA | es_ES |
dc.subject.classification | ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES | es_ES |
dc.title | Increasing the Dependability of VLSI Systems Through Early Detection of Fugacious Faults | es_ES |
dc.type | Comunicación en congreso | es_ES |
dc.identifier.doi | 10.1109/EDCC.2015.13 | |
dc.relation.projectID | info:eu-repo/grantAgreement/MINECO//TIN2012-38308-C02-01/ES/ADAPTIVE AND RESILIENT NETWORKED EMBEDDED SYSTEMS/ | es_ES |
dc.rights.accessRights | Abierto | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Departamento de Ingeniería de Sistemas y Automática - Departament d'Enginyeria de Sistemes i Automàtica | es_ES |
dc.description.bibliographicCitation | Espinosa García, J.; Andrés Martínez, DD.; Gil, P. (2015). Increasing the Dependability of VLSI Systems Through Early Detection of Fugacious Faults. IEEE Computer Society - Conference Publishing Services (CPS). https://doi.org/10.1109/EDCC.2015.13 | es_ES |
dc.description.accrualMethod | S | es_ES |
dc.relation.conferencename | 11th European Dependable Computing Conference (EDCC 2015) | es_ES |
dc.relation.conferencedate | September 7-11, 2015 | es_ES |
dc.relation.conferenceplace | Paris, France | es_ES |
dc.relation.publisherversion | http://dx.doi.org/10.1109/EDCC.2015.13 | es_ES |
dc.type.version | info:eu-repo/semantics/publishedVersion | es_ES |
dc.relation.senia | 299101 | es_ES |
dc.contributor.funder | Ministerio de Economía y Competitividad | es_ES |