Lacruz, JO.; García Herrero, FM.; Canet Subiela, MJ.; Valls Coquillat, J. (2016). High-Performance NB-LDPC Decoder With Reduction of Message Exchange. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24(5):1950-1961. https://doi.org/10.1109/TVLSI.2015.2493041
Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/66106
Título:
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High-Performance NB-LDPC Decoder With Reduction of Message Exchange
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Autor:
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Lacruz, Jesus O.
García Herrero, Francisco Miguel
Canet Subiela, Mª José
Valls Coquillat, Javier
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Entidad UPV:
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Universitat Politècnica de València. Departamento de Ingeniería Electrónica - Departament d'Enginyeria Electrònica
Universitat Politècnica de València. Instituto Universitario de Telecomunicación y Aplicaciones Multimedia - Institut Universitari de Telecomunicacions i Aplicacions Multimèdia
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Fecha difusión:
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Resumen:
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This paper presents a novel algorithm based on trellis min-max for decoding non-binary low-density parity-check (NB-LDPC) codes. This decoder reduces the number of messages exchanged between check node and variable node ...[+]
This paper presents a novel algorithm based on trellis min-max for decoding non-binary low-density parity-check (NB-LDPC) codes. This decoder reduces the number of messages exchanged between check node and variable node processors, which decreases the storage resources and the wiring congestion and, thus, increases the throughput of the decoder. Our frame error rate performance simulations show that the proposed algorithm has a negligible performance loss for high-rate codes with GF(16) and GF(32), and a performance loss smaller than 0.07 dB for high-rate codes over GF(64). In addition, a layered decoder architecture is presented and implemented on a 90-nm CMOS process for the following high-rate NB-LDPC codes: (2304, 2048) over GF(16), (837, 726) over GF(32), and (1536, 1344) over GF(64). In all cases, the achieved throughput is higher than 1 Gb/s.
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Palabras clave:
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Check node (CN) processing
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High rate
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High speed
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Layered schedule
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Non-binary low-density parity-check (NB-LDPC)
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VLSI design
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Derechos de uso:
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Reserva de todos los derechos
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Fuente:
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems. (issn:
1063-8210
) (eissn:
1557-9999
)
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DOI:
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10.1109/TVLSI.2015.2493041
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Editorial:
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Institute of Electrical and Electronics Engineers (IEEE)
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Versión del editor:
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http://dx.doi.org/10.1109/TVLSI.2015.2493041
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Código del Proyecto:
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info:eu-repo/grantAgreement/MICINN//TEC2011-27916/ES/ALGORITMOS Y ARQUITECTURAS DE FEC PARA FUTUROS SISTEMAS DE COMUNICACIONES/
info:eu-repo/grantAgreement/MINECO//TEC2012-38558-C02-02/ES/PROCESADO DIGITAL DE SEÑALES ÓPTICAS EN MEDIOS GUIADOS/
info:eu-repo/grantAgreement/GVA//GV%2F2014%2F011/
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Descripción:
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© 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
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Agradecimientos:
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This work was supported in part by the Spanish Ministerio de Ciencia e Innovacion under Grant TEC2011-27916 and Grant TEC2012-38558-C02-02, and in part by Generalitat Valenciana under Grant GV/2014/011.
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Tipo:
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Artículo
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