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dc.contributor.author | Lacruz, Jesus O. | es_ES |
dc.contributor.author | García Herrero, Francisco Miguel | es_ES |
dc.contributor.author | Canet Subiela, Mª José | es_ES |
dc.contributor.author | Valls Coquillat, Javier | es_ES |
dc.date.accessioned | 2016-06-17T15:45:16Z | |
dc.date.available | 2016-06-17T15:45:16Z | |
dc.date.issued | 2016-05 | |
dc.identifier.issn | 1063-8210 | |
dc.identifier.uri | http://hdl.handle.net/10251/66106 | |
dc.description | © 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | es_ES |
dc.description.abstract | This paper presents a novel algorithm based on trellis min-max for decoding non-binary low-density parity-check (NB-LDPC) codes. This decoder reduces the number of messages exchanged between check node and variable node processors, which decreases the storage resources and the wiring congestion and, thus, increases the throughput of the decoder. Our frame error rate performance simulations show that the proposed algorithm has a negligible performance loss for high-rate codes with GF(16) and GF(32), and a performance loss smaller than 0.07 dB for high-rate codes over GF(64). In addition, a layered decoder architecture is presented and implemented on a 90-nm CMOS process for the following high-rate NB-LDPC codes: (2304, 2048) over GF(16), (837, 726) over GF(32), and (1536, 1344) over GF(64). In all cases, the achieved throughput is higher than 1 Gb/s. | es_ES |
dc.description.sponsorship | This work was supported in part by the Spanish Ministerio de Ciencia e Innovacion under Grant TEC2011-27916 and Grant TEC2012-38558-C02-02, and in part by Generalitat Valenciana under Grant GV/2014/011. | en_EN |
dc.language | Inglés | es_ES |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | es_ES |
dc.relation.ispartof | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | es_ES |
dc.rights | Reserva de todos los derechos | es_ES |
dc.subject | Check node (CN) processing | es_ES |
dc.subject | High rate | es_ES |
dc.subject | High speed | es_ES |
dc.subject | Layered schedule | es_ES |
dc.subject | Non-binary low-density parity-check (NB-LDPC) | es_ES |
dc.subject | VLSI design | es_ES |
dc.subject.classification | TECNOLOGIA ELECTRONICA | es_ES |
dc.title | High-Performance NB-LDPC Decoder With Reduction of Message Exchange | es_ES |
dc.type | Artículo | es_ES |
dc.identifier.doi | 10.1109/TVLSI.2015.2493041 | |
dc.relation.projectID | info:eu-repo/grantAgreement/MICINN//TEC2011-27916/ES/ALGORITMOS Y ARQUITECTURAS DE FEC PARA FUTUROS SISTEMAS DE COMUNICACIONES/ | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/MINECO//TEC2012-38558-C02-02/ES/PROCESADO DIGITAL DE SEÑALES ÓPTICAS EN MEDIOS GUIADOS/ | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/GVA//GV%2F2014%2F011/ | es_ES |
dc.rights.accessRights | Abierto | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Departamento de Ingeniería Electrónica - Departament d'Enginyeria Electrònica | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Instituto Universitario de Telecomunicación y Aplicaciones Multimedia - Institut Universitari de Telecomunicacions i Aplicacions Multimèdia | es_ES |
dc.description.bibliographicCitation | Lacruz, JO.; García Herrero, FM.; Canet Subiela, MJ.; Valls Coquillat, J. (2016). High-Performance NB-LDPC Decoder With Reduction of Message Exchange. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24(5):1950-1961. https://doi.org/10.1109/TVLSI.2015.2493041 | es_ES |
dc.description.accrualMethod | S | es_ES |
dc.relation.publisherversion | http://dx.doi.org/10.1109/TVLSI.2015.2493041 | es_ES |
dc.description.upvformatpinicio | 1950 | es_ES |
dc.description.upvformatpfin | 1961 | es_ES |
dc.type.version | info:eu-repo/semantics/publishedVersion | es_ES |
dc.description.volume | 24 | es_ES |
dc.description.issue | 5 | es_ES |
dc.relation.senia | 307670 | es_ES |
dc.identifier.eissn | 1557-9999 | |
dc.contributor.funder | Generalitat Valenciana | es_ES |
dc.contributor.funder | Ministerio de Economía y Competitividad | es_ES |
dc.contributor.funder | Ministerio de Ciencia e Innovación | es_ES |