- -

A 630 Mbps non-binary decoder for FPGA

RiuNet: Institutional repository of the Polithecnic University of Valencia

Share/Send to

Cited by


A 630 Mbps non-binary decoder for FPGA

Show full item record

Lacruz Jucht, JO.; García Herrero, FM.; Canet Subiela, MJ.; Valls Coquillat, J.; Pérez Pascual, MA. (2015). A 630 Mbps non-binary decoder for FPGA. IEEE. doi:10.1109/ISCAS.2015.7169065

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/70703

Files in this item

Item Metadata

Title: A 630 Mbps non-binary decoder for FPGA
Author: Lacruz Jucht, Jesús Omar García Herrero, Francisco Miguel Canet Subiela, Mª José Valls Coquillat, Javier Pérez Pascual, Mª Asunción
UPV Unit: Universitat Politècnica de València. Escuela Politécnica Superior de Gandia - Escola Politècnica Superior de Gandia
Universitat Politècnica de València. Departamento de Ingeniería Electrónica - Departament d'Enginyeria Electrònica
Issued date:
A high-speed non-binary LDPC decoder based on Trellis Min-Max algorithm with layered schedule is presented. The proposed approach compresses the check-node output messages into a reduced set, decreasing the number of ...[+]
Subjects: Non-binary LDPC , Decoder , FPGA
Copyrigths: Reserva de todos los derechos
ISBN: 978-147998391-9
IEEE International Symposium on Circuits and Systems. (issn: 0271-4310 )
DOI: 10.1109/ISCAS.2015.7169065
Publisher version: http://dx.doi.org/10.1109/ISCAS.2015.7169065
Conference name: IEEE International Symposium on Circuits and Systems (ISCAS 2015)
Conference place: Lisboa
Conference date: 2015-05-24
Project ID:
This work was supported in part by the Universidad Politécnica de Valencia under Grant PAID-06-2012-SP20120625, in part by the Spanish Ministerio de Ciencia e Innovación under Grant TEC2011-27916 and in part by the Generalitat ...[+]
Type: Comunicación en congreso

This item appears in the following Collection(s)

Show full item record