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A 630 Mbps non-binary decoder for FPGA

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A 630 Mbps non-binary decoder for FPGA

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Lacruz Jucht, JO.; García Herrero, FM.; Canet Subiela, MJ.; Valls Coquillat, J.; Pérez Pascual, MA. (2015). A 630 Mbps non-binary decoder for FPGA. IEEE. doi:10.1109/ISCAS.2015.7169065

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/70703

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Title: A 630 Mbps non-binary decoder for FPGA
Author:
UPV Unit: Universitat Politècnica de València. Escuela Politécnica Superior de Gandia - Escola Politècnica Superior de Gandia
Universitat Politècnica de València. Departamento de Ingeniería Electrónica - Departament d'Enginyeria Electrònica
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Abstract:
A high-speed non-binary LDPC decoder based on Trellis Min-Max algorithm with layered schedule is presented. The proposed approach compresses the check-node output messages into a reduced set, decreasing the number of ...[+]
Subjects: Non-binary LDPC , Decoder , FPGA
Copyrigths: Reserva de todos los derechos
ISBN: 978-147998391-9
Source:
IEEE International Symposium on Circuits and Systems. (issn: 0271-4310 )
DOI: 10.1109/ISCAS.2015.7169065
Publisher:
IEEE
Publisher version: http://dx.doi.org/10.1109/ISCAS.2015.7169065
Conference name: IEEE International Symposium on Circuits and Systems (ISCAS 2015)
Conference place: Lisboa
Conference date: 2015-05-24
Type: Comunicación en congreso

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