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A 630 Mbps non-binary decoder for FPGA

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A 630 Mbps non-binary decoder for FPGA

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dc.contributor.author Lacruz Jucht, Jesús Omar es_ES
dc.contributor.author García Herrero, Francisco Miguel es_ES
dc.contributor.author Canet Subiela, Mª José es_ES
dc.contributor.author Valls Coquillat, Javier es_ES
dc.contributor.author Pérez Pascual, Mª Asunción es_ES
dc.date.accessioned 2016-09-29T16:44:11Z
dc.date.available 2016-09-29T16:44:11Z
dc.date.issued 2015-07
dc.identifier.isbn 978-147998391-9
dc.identifier.issn 0271-4310
dc.identifier.uri http://hdl.handle.net/10251/70703
dc.description.abstract A high-speed non-binary LDPC decoder based on Trellis Min-Max algorithm with layered schedule is presented. The proposed approach compresses the check-node output messages into a reduced set, decreasing the number of messages sent to the variable node. Additionally, the memory resources from the layered architecture are reduced. The proposed decoder was implemented for the (2304,2048) NB-LDPC code over GF(16) on a Virtex-7 FPGA and in a 90 nm CMOS process. Our implementation outperforms state-of-the-art NB-LDPC decoder implementations for both technologies, achieving a throughput of 630 and 965 Mbps, respectively. es_ES
dc.description.sponsorship This work was supported in part by the Universidad Politécnica de Valencia under Grant PAID-06-2012-SP20120625, in part by the Spanish Ministerio de Ciencia e Innovación under Grant TEC2011-27916 and in part by the Generalitat Valenciana under Grant GV/2014/011. es_ES
dc.language Inglés es_ES
dc.publisher IEEE es_ES
dc.relation MICINN/TEC2011-27916 es_ES
dc.relation UPV/PAID/SP20120625 es_ES
dc.relation GV/2014/011 es_ES
dc.relation.ispartof IEEE International Symposium on Circuits and Systems
dc.rights Reserva de todos los derechos es_ES
dc.subject Non-binary LDPC es_ES
dc.subject Decoder es_ES
dc.subject FPGA es_ES
dc.subject.classification TECNOLOGIA ELECTRONICA es_ES
dc.title A 630 Mbps non-binary decoder for FPGA es_ES
dc.type Comunicación en congreso es_ES
dc.identifier.doi 10.1109/ISCAS.2015.7169065
dc.rights.accessRights Abierto es_ES
dc.contributor.affiliation Universitat Politècnica de València. Escuela Politécnica Superior de Gandia - Escola Politècnica Superior de Gandia es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Ingeniería Electrónica - Departament d'Enginyeria Electrònica es_ES
dc.description.bibliographicCitation Lacruz Jucht, JO.; García Herrero, FM.; Canet Subiela, MJ.; Valls Coquillat, J.; Pérez Pascual, MA. (2015). A 630 Mbps non-binary decoder for FPGA. IEEE. doi:10.1109/ISCAS.2015.7169065 es_ES
dc.description.accrualMethod Senia es_ES
dc.relation.conferencename IEEE International Symposium on Circuits and Systems (ISCAS 2015) es_ES
dc.relation.conferencedate 2015-05-24 es_ES
dc.relation.conferenceplace Lisboa es_ES
dc.relation.publisherversion http://dx.doi.org/10.1109/ISCAS.2015.7169065 es_ES
dc.type.version info:eu-repo/semantics/publishedVersion es_ES
dc.relation.senia 301935 es_ES
dc.contributor.funder Universitat Politècnica de València es_ES
dc.contributor.funder Ministerio de Ciencia e Innovación es_ES
dc.contributor.funder Generalitat Valenciana es_ES


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