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Bandwidth-Aware On-Line Scheduling in SMT Multicores

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Feliu-Pérez, J.; Sahuquillo Borrás, J.; Petit Martí, SV.; Duato Marín, JF. (2016). Bandwidth-Aware On-Line Scheduling in SMT Multicores. IEEE Transactions on Computers. 65(2):422-434. doi:10.1109/TC.2015.2428694

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/81480

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Title: Bandwidth-Aware On-Line Scheduling in SMT Multicores
UPV Unit: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Universitat Politècnica de València. Escola Tècnica Superior d'Enginyeria Informàtica
Issued date:
The memory hierarchy plays a critical role on the performance of current chip multiprocessors. Main memory is shared by all the running processes, which can cause important bandwidth contention. In addition, when the ...[+]
Subjects: Bandwidth-aware scheduling , Process selection , Process allocation , L1-bandwidth , Bandwidth contention , SMT
Copyrigths: Reserva de todos los derechos
IEEE Transactions on Computers. (issn: 0018-9340 )
DOI: 10.1109/TC.2015.2428694
Institute of Electrical and Electronics Engineers (IEEE)
Publisher version: http://dx.doi.org/10.1109/TC.2015.2428694
Description: © 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
This work was supported by the Spanish Ministerio de Economia y Competitividad (MINECO) and by FEDER funds under Grant TIN2012-38341-C04-01, and by the Intel Early Career Faculty Honor Program Award.
Type: Artículo

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