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Out-of-Order Retirement of Instructions in Superscalar, Multithreaded, and Multicore Processors

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Out-of-Order Retirement of Instructions in Superscalar, Multithreaded, and Multicore Processors

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Ubal Tena, R. (2010). Out-of-Order Retirement of Instructions in Superscalar, Multithreaded, and Multicore Processors [Tesis doctoral no publicada]. Universitat Politècnica de València. doi:10.4995/Thesis/10251/8535.

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Title: Out-of-Order Retirement of Instructions in Superscalar, Multithreaded, and Multicore Processors
Author:
Director(s): Sahuquillo Borrás, Julio López Rodríguez, Pedro Juan
UPV Unit: Universitat Politècnica de València. Departamento de Sistemas Informáticos y Computación - Departament de Sistemes Informàtics i Computació
Read date / Event date:
2010-07-06
Issued date:
Abstract:
Los procesadores superescalares actuales utilizan un reorder buffer (ROB) para contabilizar las instrucciones en vuelo. El ROB se implementa como una cola FIFO first in first out en la que las instrucciones se insertan en ...[+]
Subjects: Out-of-order retirement , Reorder buffer , Processor architecture , Multithreading , Multicore , Superscalar , Sequential consistency
UNESCO code: 120317 - Informática
120326 - Simulación
330406 - Arquitectura de ordenadores
Copyrigths: Reserva de todos los derechos
DOI: 10.4995/Thesis/10251/8535
Type: Tesis doctoral

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