Feliu Pérez, Josué(Universitat Politècnica de València, 2013-02-25)
[ES] Con el objetivo de mejorar el rendimiento de los CMPs, parte de la investigación reciente se ha centrado en la planificación de procesos para limitar la contención provocada por el limitado ancho de banda. Hoy en dia, ...
Naithani, Ajeya; Feliu-Pérez, Josué; Adileh, Almutaz; Eeckhout, Lieven(Institute of Electrical and Electronics Engineers, 2019-06)
[EN] Runahead execution improves processor performance by accurately prefetching long-latency memory accesses. When a long-latency load causes the instruction window to fill up and halt the pipeline, the processor enters ...
Navarro Serra, Carlos(Universitat Politècnica de València, 2018-09-10)
[ES] Hoy en día, los procesadores implementan una serie de prefetchers a lo largo de la
jerarquía de caché del procesador con el objetivo de reducir u ocultar la latencia de los
accesos a memoria y, con ello, mejorar las ...
Navarro Serra, Carlos(Universitat Politècnica de València, 2019-07-30)
[ES] La mejora de las prestaciones del subsistema de memoria RAM (jerarquía de cache y memoria principal) es uno de los grandes retos en que se han centrado muchos de los trabajos recientes para incrementar las prestaciones ...
[EN] Superscalar out-of-order cores deliver high performance at the cost of increased complexity and power budget. In-order cores, in contrast, are less complex and have a smaller power budget, but offer low performance. ...
Feliu-Pérez, Josué; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Eeckhout, Lieven(Institute of Electrical and Electronics Engineers, 2020-02-01)
[EN] Resource sharing is a critical issue in simultaneous multithreading (SMT) processors as threads running simultaneously on an SMT core compete for shared resources. Symbiotic job scheduling, which co-schedules applications ...
Feliu Pérez, Josué; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Duato Marín, José Francisco(IEEE, 2012-05-21)
In order to improve CMP performance, recent research has focused on scheduling to mitigate contention produced by the limited memory bandwidth. Nowadays, commercial CMPs implement multi-level cache hierarchies where last ...
Pons-Escat, Lucía; Feliu-Pérez, Josué; Puche, José; Huang, Chaoyi; Petit Martí, Salvador Vicente; Pons Terol, Julio; Gómez Requena, María Engracia; Sahuquillo, Julio(Cornell University, 2020-10)
[EN] Understanding inter-VM interference is of paramount importance to provide a sound knowledge and understand where performance
degradation comes from in the current public cloud. With this aim, this paper devises a ...
Feliu Pérez, Josué; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Duato Marín, José Francisco(Elsevier, 2013-06)
Performance of current chip multiprocessors (CMPs) is strongly connected with the performance of their last level caches (LLCs), which mainly depends on the cache requirements of the processes as well as their interference. ...
Feliu-Pérez, Josué; Naithani, Ajeya; Sahuquillo Borrás, Julio; Petit Martí, Salvador Vicente; Qureshi, Moinuddin; Eeckhout, Lieven(Institute of Electrical and Electronics Engineers, 2022-06-01)
[EN] Modern-day graph workloads operate on huge graphs through pointer chasing which leads to high last-level cache (LLC) miss rates and limited memory-level parallelism (MLP). Simultaneous Multi-Threading (SMT) effectively ...