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Using huge pages and performance counters to determine the LLC architecture

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Using huge pages and performance counters to determine the LLC architecture

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Feliu Pérez, J.; Sahuquillo Borrás, J.; Petit Martí, SV.; Duato Marín, JF. (2013). Using huge pages and performance counters to determine the LLC architecture. Procedia Computer Science. 18:2557-2560. doi:10.1016/j.procs.2013.05.440

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/70449

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Title: Using huge pages and performance counters to determine the LLC architecture
Author:
UPV Unit: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Universitat Politècnica de València. Escola Tècnica Superior d'Enginyeria Informàtica
Issued date:
Abstract:
Performance of current chip multiprocessors (CMPs) is strongly connected with the performance of their last level caches (LLCs), which mainly depends on the cache requirements of the processes as well as their interference. ...[+]
Subjects: Cache architecture , Cache geometry , Huge pages , Performance counters , LLC
Copyrigths: Reserva de todos los derechos
Source:
Procedia Computer Science. (issn: 1877-0509 )
DOI: 10.1016/j.procs.2013.05.440
Publisher:
Elsevier
Publisher version: http://dx.doi.org/10.1016/j.procs.2013.05.440
Conference name: International Conference on Computational Science (ICCS 2013): "Computation at the Frontiers of Science"
Conference place: Barcelona
Conference date: 2013-06-05
Project ID: info:eu-repo/grantAgreement/EC/FP7/287759/EU
Type: Artículo Comunicación en congreso

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