Using huge pages and performance counters to determine the LLC architecture

Abstract

Performance of current chip multiprocessors (CMPs) is strongly connected with the performance of their last level caches (LLCs), which mainly depends on the cache requirements of the processes as well as their interference. To effectively address such issues, researchers should be aware of the features of LLCs when performing research on real systems. Consequently, some research works have focused on experimentally determining such features, although most existing proposals take assumptions that are not met in current LLCs. To achieve this goal in real machines, we devised three tests that make use of huge pages to control the accessed cache sets, and performance counters to monitor the LLC behavior. The presented tests can be used in many experimental cache-aware research works; for instance in the design of thread scheduling policies.