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dc.contributor.author | Iriondo, Nagore![]() |
es_ES |
dc.contributor.author | Estévez, Elisabet![]() |
es_ES |
dc.contributor.author | Priego, Rafael![]() |
es_ES |
dc.contributor.author | Marcos, Marga![]() |
es_ES |
dc.date.accessioned | 2020-05-21T11:51:29Z | |
dc.date.available | 2020-05-21T11:51:29Z | |
dc.date.issued | 2013-04-07 | |
dc.identifier.issn | 1697-7912 | |
dc.identifier.uri | http://hdl.handle.net/10251/143994 | |
dc.description.abstract | [ES] Los sistemas con conmutación de modos se definen como aquéllos que pueden exhibir diferente comportamiento dinámico en función del estado en que se encuentran. Pueden por tanto ser descritos por un conjunto finito de subsistemas dinámicos y una lógica que rige la conmutación entre ellos. Una alternativa para su control es la arquitectura multi-controlador con supervisión ya que permite utilizar controladores de modo diferentes y alcanzar así múltiples objetivos de control. Pero la conmutación de controladores suele tener como consecuencia la aparición de saltos o transitorios derivados que pueden ser inaceptables. Este tipo de sistemas y problemática son frecuentes en diferentes áreas de aplicación industrial, en donde la tecnología de control más utilizada es el Controlador Lógico Programable (PLC). Es por ello que el objetivo de este trabajo es presentar un método de diseño e implementación de un mecanismo de transferencia sin salto (BT) en una arquitectura multi-modo y multi-bucle para sistemas con conmutación de modos, en PLC y en conformidad con el estándar IEC 61131-3. La estrategia BT se basa en que controladores de modos candidatos a conmutar realicen un seguimiento a los controladores activos, siendo la detección del estado de operación actual y de los posibles estados siguientes, clave en la definición de la forma de ejecución de los algoritmos de control que componen la arquitectura. Se presentan también los pasos del diseño de la arquitectura completa así como resultados experimentales que validan la arquitectura. | es_ES |
dc.description.abstract | [EN] Switched mode systems are defined as those represented by a finite set of linear subsystems and a set of logic rules orchestrating the switching among them. A set of dynamic subsystems together with a logical system that orchestrates the switching among them could be used in order to describe it. An alternative to control them is a supervisory multi-mode controller architecture that allows to meeting multiple control objectives. But switching can consequently derived in bumps or undesirable transient responses. This type of problem is commonly encountered in several industrial application fields, where the Programmable Logic Controller (PLCs) is the most used technology. This paper describes a methodology for the design and the implementation of Bumpless Transfer (BT) mechanisms within multi-rate control architecture for switched mode systems, to be implemented in PLC following the IEC 61131-3 standard. The BT strategy is based on to make controllers which are candidate to switch track to active controllers. By detecting the system state and the feasible next states, the supervisor decides the way in which the different controllers of the architecture execute. The steps to design the complete architecture are presented and experimental results that validate the architecture are shown. | es_ES |
dc.description.sponsorship | MCYT y FEDER a través de los proyectos DPI2012-37806-C02-01, UPV/EHU GIU 10/20 y UFI11/28. | es_ES |
dc.language | Español | es_ES |
dc.publisher | Universitat Politècnica de València | es_ES |
dc.relation.ispartof | Revista Iberoamericana de Automática e Informática industrial | es_ES |
dc.rights | Reconocimiento - No comercial - Sin obra derivada (by-nc-nd) | es_ES |
dc.subject | Switched-mode systems | es_ES |
dc.subject | Supervision | es_ES |
dc.subject | Time-driven scheduling | es_ES |
dc.subject | Bumpless Transfer | es_ES |
dc.subject | IEC 61131-3 standard | es_ES |
dc.subject | Sistemas con conmutación de modos | es_ES |
dc.subject | Supervisión | es_ES |
dc.subject | Planificación conducida por tiempo | es_ES |
dc.subject | Estándar IEC 61131-3 | es_ES |
dc.title | Arquitectura multi-controlador con transferencia sin salto para procesos con conmutación de modos | es_ES |
dc.title.alternative | A multi-controller with bumpless transfer architecture for industrial switched-mode processes | es_ES |
dc.type | Artículo | es_ES |
dc.identifier.doi | 10.1016/j.riai.2013.03.010 | |
dc.relation.projectID | info:eu-repo/grantAgreement/MINECO//DPI2012-37806-C02-01/ES/APLICACIONES DE FABRICACION RECONFIGURABLES DIRIGIDAS POR REQUISITOS DE QOS/ | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/UPV%2FEHU//GIU10%2F20/ | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/UPV%2FEHU//UFI11%2F28/ | es_ES |
dc.rights.accessRights | Abierto | es_ES |
dc.description.bibliographicCitation | Iriondo, N.; Estévez, E.; Priego, R.; Marcos, M. (2013). Arquitectura multi-controlador con transferencia sin salto para procesos con conmutación de modos. Revista Iberoamericana de Automática e Informática industrial. 10(2):204-215. https://doi.org/10.1016/j.riai.2013.03.010 | es_ES |
dc.description.accrualMethod | OJS | es_ES |
dc.relation.publisherversion | https://doi.org/10.1016/j.riai.2013.03.010 | es_ES |
dc.description.upvformatpinicio | 204 | es_ES |
dc.description.upvformatpfin | 215 | es_ES |
dc.type.version | info:eu-repo/semantics/publishedVersion | es_ES |
dc.description.volume | 10 | es_ES |
dc.description.issue | 2 | es_ES |
dc.identifier.eissn | 1697-7920 | |
dc.relation.pasarela | OJS\9546 | es_ES |
dc.contributor.funder | Ministerio de Economía y Competitividad | es_ES |
dc.contributor.funder | Universidad del País Vasco/Euskal Herriko Unibertsitatea | es_ES |
dc.contributor.funder | European Regional Development Fund | es_ES |
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