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Parametric Timing Analisys and Its Appication to Dynamic Voltage Scaling

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Parametric Timing Analisys and Its Appication to Dynamic Voltage Scaling

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dc.contributor.author Mohan, S. es_ES
dc.contributor.author Mueller, F. es_ES
dc.contributor.author Root, M. es_ES
dc.contributor.author Hawkins, W. es_ES
dc.contributor.author Healy, C. es_ES
dc.contributor.author Whalley, D. es_ES
dc.contributor.author Vivancos Rubio, Emilio es_ES
dc.date.accessioned 2013-07-01T10:47:50Z
dc.date.issued 2011
dc.identifier.issn 1539-9087
dc.identifier.uri http://hdl.handle.net/10251/30308
dc.description.abstract Embedded systems with real-time constraints depend on a priori knowledge of worst-case execution times (WCETs) to determine if tasks meet deadlines. Static timing analysis derives bounds on WCETs but requires statically known loop bounds. This work removes the constraint on known loop bounds through parametric analysis expressing WCETs as functions. Tighter WCETs are dynamically discovered to exploit slack by dynamic voltage scaling (DVS) saving 60% to 82% energy over DVS-oblivious techniques and showing savings close to more costly dynamic-priority DVS algorithms. Overall, parametric analysis expands the class of real-time applications to programs with loop-invariant dynamic loop bounds while retaining tight WCET bounds. es_ES
dc.description.sponsorship This work was conducted at North Carolina State University and Florida State University; it was supported in part by NSF grants CCR-0208581, CCR-0310860, CCR-0312695, EIA-0072043, CCR-0208892, CCR-0312493 and CCR-0312531. en_EN
dc.language Inglés es_ES
dc.publisher Association for Computing Machinery (ACM) es_ES
dc.relation NSF CCR-0208581 CCR-0310860 CCR-0312695 EIA-0072043 CCR-0208892 CCR-0312493 CCR-0312531 es_ES
dc.relation.ispartof ACM Transactions on Embedded Computing Systems es_ES
dc.rights Reserva de todos los derechos es_ES
dc.subject Algorithms es_ES
dc.subject Experimentation es_ES
dc.subject Real-time systems es_ES
dc.subject Worst-case execution time es_ES
dc.subject Timing analysis es_ES
dc.subject Dynamic voltage scaling es_ES
dc.subject.classification LENGUAJES Y SISTEMAS INFORMATICOS es_ES
dc.title Parametric Timing Analisys and Its Appication to Dynamic Voltage Scaling es_ES
dc.type Artículo es_ES
dc.embargo.lift 10000-01-01
dc.embargo.terms forever es_ES
dc.identifier.doi 10.1145/1880050.1880061
dc.rights.accessRights Cerrado es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Sistemas Informáticos y Computación - Departament de Sistemes Informàtics i Computació es_ES
dc.description.bibliographicCitation Mohan, S.; Mueller, F.; Root, M.; Hawkins, W.; Healy, C.; Whalley, D.; Vivancos Rubio, E. (2011). Parametric Timing Analisys and Its Appication to Dynamic Voltage Scaling. ACM Transactions on Embedded Computing Systems. 10(2):1-34. doi:10.1145/1880050.1880061 es_ES
dc.description.accrualMethod Senia es_ES
dc.relation.publisherversion http://dx.doi.org/10.1145/1880050.1880061 es_ES
dc.description.upvformatpinicio 1 es_ES
dc.description.upvformatpfin 34 es_ES
dc.type.version info:eu-repo/semantics/publishedVersion es_ES
dc.description.volume 10 es_ES
dc.description.issue 2 es_ES
dc.relation.senia 41530


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