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dc.contributor.author | García Herrero, Francisco Miguel![]() |
es_ES |
dc.contributor.author | Canet Subiela, Mª José![]() |
es_ES |
dc.contributor.author | Valls Coquillat, Javier![]() |
es_ES |
dc.contributor.author | Meher, Pramod Kumar![]() |
es_ES |
dc.date.accessioned | 2014-02-10T19:46:57Z | |
dc.date.issued | 2012-03 | |
dc.identifier.issn | 1063-8210 | |
dc.identifier.uri | http://hdl.handle.net/10251/35462 | |
dc.description.abstract | In this paper, a high-throughput interpolator architecture for soft-decision decoding of Reed-Solomon (RS) codes based on low-complexity chase (LCC) decoding is presented. We have formulated a modified form of the Nielson's interpolation algorithm, using some typical features of LCC decoding. The proposed algorithm works with a different scheduling, takes care of the limited growth of the polynomials, and shares the common interpolation points, for reducing the latency of interpolation. Based on the proposed modified Nielson's algorithm we have derived a low-latency architecture to reduce the overall latency of the whole LCC decoder. An efficiency of at least 39%, in terms of area-delay product, has been achieved by an LCC decoder, by using the proposed interpolator architecture, over the best of the previously reported architectures for an RS(255,239) code with eight test vectors. We have implemented the proposed interpolator in a Virtex-II FPGA device, which provides 914 Mb/s of throughput using 806 slices. © 2011 IEEE. | es_ES |
dc.description.sponsorship | This work was supported by FEDER and the Spanish Ministerio de Ciencia e Innovacion, under Grant TEC2008-06787. | en_EN |
dc.format.extent | 6 | es_ES |
dc.language | Inglés | es_ES |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | es_ES |
dc.relation.ispartof | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | es_ES |
dc.rights | Reserva de todos los derechos | es_ES |
dc.subject | Algebraic soft-decision decoding | es_ES |
dc.subject | Interpolation | es_ES |
dc.subject | Low-complexity chase (LCC) | es_ES |
dc.subject | Low latency | es_ES |
dc.subject | Nielson's algorithm | es_ES |
dc.subject | Reed-Solomon (R-S) codes | es_ES |
dc.subject.classification | TECNOLOGIA ELECTRONICA | es_ES |
dc.title | High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes | es_ES |
dc.type | Artículo | es_ES |
dc.embargo.lift | 10000-01-01 | |
dc.embargo.terms | forever | es_ES |
dc.identifier.doi | 10.1109/TVLSI.2010.2103961 | es_ES |
dc.relation.projectID | info:eu-repo/grantAgreement/MICINN//TEC2008-06787/ES/ARQUITECTURAS DE FEC PARA SISTEMAS DE COMUNICACIONES DE MUY ALTA VELOCIDAD/ | es_ES |
dc.rights.accessRights | Cerrado | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Departamento de Ingeniería Electrónica - Departament d'Enginyeria Electrònica | es_ES |
dc.contributor.affiliation | Universitat Politècnica de València. Instituto Universitario de Telecomunicación y Aplicaciones Multimedia - Institut Universitari de Telecomunicacions i Aplicacions Multimèdia | es_ES |
dc.description.bibliographicCitation | García Herrero, FM.; Canet Subiela, MJ.; Valls Coquillat, J.; Meher, PK. (2012). High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20(3):568-573. https://doi.org/10.1109/TVLSI.2010.2103961 | es_ES |
dc.description.accrualMethod | S | es_ES |
dc.relation.publisherversion | http://dx.doi.org/10.1109/TVLSI.2010.2103961 | es_ES |
dc.description.upvformatpinicio | 568 | es_ES |
dc.description.upvformatpfin | 573 | es_ES |
dc.type.version | info:eu-repo/semantics/publishedVersion | es_ES |
dc.description.volume | 20 | es_ES |
dc.description.issue | 3 | es_ES |
dc.relation.senia | 212853 | |
dc.contributor.funder | Ministerio de Ciencia e Innovación | es_ES |
dc.contributor.funder | European Regional Development Fund | es_ES |