- -

A communication-driven routing technique for application-specific NoCs

RiuNet: Repositorio Institucional de la Universidad Politécnica de Valencia

Compartir/Enviar a

Citas

Estadísticas

  • Estadisticas de Uso

A communication-driven routing technique for application-specific NoCs

Mostrar el registro completo del ítem

Tornero, R.; Orduña Huertas, JM.; Mejia, A.; Flich Cardo, J.; Duato Marín, JF. (2011). A communication-driven routing technique for application-specific NoCs. International Journal of Parallel Programming. 39(3):357-374. https://doi.org/10.1007/s10766-010-0159-9

Por favor, use este identificador para citar o enlazar este ítem: http://hdl.handle.net/10251/37055

Ficheros en el ítem

Metadatos del ítem

Título: A communication-driven routing technique for application-specific NoCs
Autor: Tornero, Rafael Orduña Huertas, Juan Manuel Mejia, Andres Flich Cardo, José Duato Marín, José Francisco
Entidad UPV: Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors
Fecha difusión:
Resumen:
Networks on Chip (NoCs) have been shown as an efficient solution to the complex on-chip communication problems derived from the increasing number of processor cores. One of the key issues in the design of NoCs is the ...[+]
Palabras clave: Networks-on-chip , Topology-agnostic routing , Topological mapping
Derechos de uso: Cerrado
Fuente:
International Journal of Parallel Programming. (issn: 0885-7458 )
DOI: 10.1007/s10766-010-0159-9
Editorial:
Springer Verlag (Germany)
Versión del editor: http://link.springer.com/article/10.1007%2Fs10766-010-0159-9
Código del Proyecto:
info:eu-repo/grantAgreement/MEC//CSD2006-00046/ES/Arquitecturas fiables y de altas prestaciones para centros de proceso de datos y servidores de Internet/
info:eu-repo/grantAgreement/EC/FP7/217068/EU/High Performance and Embedded Architecture and Compilation/
info:eu-repo/grantAgreement/MICINN//TIN2009-14475-C04-04/ES/Arquitecturas De Servidores, Aplicaciones Y Servicios./
Descripción: The final publication is available at Springer via http://dx.doi.org/10.1007/s10766-010-0159-9
Agradecimientos:
This work has been jointly supported by the Spanish MICINN, the European Commission FEDER funds, and the University of Valencia under grants Consolider-Ingenio 2010 CSD2006-00046, TIN2009-14475-C04-04, and V_SEGLES_PIE.
Tipo: Artículo

References

Duato, J., Yalamanchili, S., Ni, L.: Interconnection Networks an Engineering Approach. IEEE Computer Society (2003)

Mak, T.S.T., Sedcole, P., Cheung, P.Y.K., Luk, W., Lam, K.P.: A hybrid analog-digital routing network for noc dynamic routing. In: NOCS ’07: Proceedings of the First International Symposium on Networks-on-Chip, pp. 173–182. IEEE Computer Society, Washington, DC, USA (2007)

Sancho, J.C., Robles, A., Flich, J., Lopez, P., Duato, J.: Effective methodology for deadlock-free minimal routing in infiniband networks. In: Proceedings of the 2002 International Conference on Parallel Processing. IEEE Computer Society (2002) [+]
Duato, J., Yalamanchili, S., Ni, L.: Interconnection Networks an Engineering Approach. IEEE Computer Society (2003)

Mak, T.S.T., Sedcole, P., Cheung, P.Y.K., Luk, W., Lam, K.P.: A hybrid analog-digital routing network for noc dynamic routing. In: NOCS ’07: Proceedings of the First International Symposium on Networks-on-Chip, pp. 173–182. IEEE Computer Society, Washington, DC, USA (2007)

Sancho, J.C., Robles, A., Flich, J., Lopez, P., Duato, J.: Effective methodology for deadlock-free minimal routing in infiniband networks. In: Proceedings of the 2002 International Conference on Parallel Processing. IEEE Computer Society (2002)

Skeie, T., Lysne, O., Flich, J., Lopez, P., Robles, A., Duato, J.: Lash-tor: A generic transition-oriented routing algorithm. In: Proceedings of IEEE International Conference on Parallel and Distributed Systems. IEEE Computer Society (2004)

Schroeder M.D., Birrell A.D., Burrows M., Murray H., Needham R.M., Rodeheffer T.L.: Autonet: A high-speed, self-configuring local area network using point-to-point links. IEEE J. Sel. Areas Commun. 9(8), 1318–1335 (1991)

Sancho, J.C., Robles, A., Duato, J.: A flexible routing scheme for networks of workstations. In: Proceedings of 2000 International Conference on High Performance Computing. IEEE Computer Society (2000)

Koibuchi, M., Jouraku, A., Watanabe, K., Amano, H.: Descending layers routing: A deadlock-free deterministic routing using virtual channels in system area networks with irregular topologies. In: Proceedings International Conference on Parallel Processing. IEEE Computer Society (2003)

Mejia, A., Flich, J., Duato, J., Reinemo, S., Skeie, T.: Segment-based routing: An efficient fault-tolerant routing algorithm for meshes and tori. In: International Parallel and Distributed Processing Symposium: 20th IPDPS 2006, Rhodos-Grece (2006)

Mejia, A., Flich, J., Duato, J.: On the potentials of segment-based routing for nocs. In: ICPP ’08. 37th International Conference on Parallel Processing, 2008, pp. 594–603. (2008)

Orduña J., Silla F., Duato J.: On the development of a communication-aware task mapping technique. J. Syst. Archit. 50(4), 207–220 (2004)

Tornero, R., Orduña, J.M., Palesi, M., Duato, J.: A communication-aware topological mapping technique for nocs. In: Euro-Par 2008: Proceedings of the 14th International Euro-Par Conference on Parallel Processing. Lecture Notes on Computer Science, vol. 5168, pp. 910–919. Springer, Berlin, Heidelberg (2008)

Tornero, R., Orduña, J.M., Mejía, A., Flich, J., Duato, J.: Cart: Communication-aware routing technique for application-specific nocs. In: Fanucci, L. (ed.) 11th EuroMicro Conference on Digital System Design. (2008)

Ann Gordon-Ross, N.D., Vahid, F.: Fast configurable-cache tuning with a unified second-level cache. In: International Symposium on Low-Power Electronics and Design, pp. 323–326. (2005)

Ascia G., Catania V., Palesi M.: A multi-objective genetic approach for system-level exploration in parameterized systems-on-a-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4), 635–645 (2005)

Benini L., Macii A., Macii E., Poncino M., Scarsi R.: Architectures and synthesis algorithms for power-efficient bus interfaces. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(9), 969–980 (2000)

Palesi, M., Holsmark, R., Kumar, S., Catania, V.: A methodology for design of application specific deadlock-free routing algorithms for noc systems. In: CODES+ISSS ’06: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, pp. 142–147. ACM Press, New York, NY, USA (2006)

Ascia G., Catania V., Palesi M.: Mapping cores on network–on–chip. Int. J. Comput. Intell. Res. 1(1–2), 109–126 (2005)

Hu J., Marculescu R.: Energy- and performance-aware mapping for regular NoC architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4), 551–562 (2005)

Noxim, Network-on-Chip simulator. In: http://noxim.sourceforge.net

[-]

recommendations

 

Este ítem aparece en la(s) siguiente(s) colección(ones)

Mostrar el registro completo del ítem