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Characterizing the impact of process variation on 45 nm NoC-based CMPs

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Characterizing the impact of process variation on 45 nm NoC-based CMPs

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dc.contributor.author Hernández Luz, Carles es_ES
dc.contributor.author Roca Pérez, Antoni es_ES
dc.contributor.author Flich Cardo, José es_ES
dc.contributor.author Silla Jiménez, Federico es_ES
dc.contributor.author Duato Marín, José Francisco es_ES
dc.date.accessioned 2014-05-23T07:08:36Z
dc.date.issued 2011-05
dc.identifier.issn 0743-7315
dc.identifier.uri http://hdl.handle.net/10251/37694
dc.description.abstract [EN] Current integration scales make possible to design chip multiprocessors with a large amount of cores interconnected by a NoC. Unfortunately, they also bring process variation, posing a new burden to processor manufacturers. Regarding the NoC, variability causes that the delays of links and routers do not match those initially established at design time. In this paper we analyze how variability affects the NoC by applying a new variability model to 100 instances of an 8 ¿ 8 mesh NoC synthesized using 45 nm technology. We also show that GALS-based NoCs present communication bottlenecks due to the slower components of the network, which cause congestion, thus reducing performance. This performance reduction finally affects the applications being executed in the CMP because they may be mapped to slower areas of the chip. In this paper we show that using a mapping algorithm that considers variability data may improve application execution time up to 50%. © 2010 Elsevier Inc. All rights reserved. es_ES
dc.description.sponsorship This work was supported by the Spanish MEC and MICINN, as well as European Comission FEDER funds, under Grants CSD2006-00046 and TIN2009-14475-C04. It was also partly supported by the project NaNoC (project label 248972) which is funded by the European Commission within the Research Programme FP7. en_EN
dc.format.extent 13 es_ES
dc.language Inglés es_ES
dc.publisher Elsevier es_ES
dc.relation.ispartof Journal of Parallel and Distributed Computing es_ES
dc.rights Reserva de todos los derechos es_ES
dc.subject CMP (or Chip multiprocessor) es_ES
dc.subject NoC (or Network-on-Chip) es_ES
dc.subject Process mapping es_ES
dc.subject Process variations es_ES
dc.subject Router design es_ES
dc.subject Chip Multiprocessor es_ES
dc.subject Conformal mapping es_ES
dc.subject Design es_ES
dc.subject Microprocessor chips es_ES
dc.subject Multiprocessing systems es_ES
dc.subject Servers es_ES
dc.subject Systems analysis es_ES
dc.subject VLSI circuits es_ES
dc.subject Routers es_ES
dc.subject.classification ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES es_ES
dc.title Characterizing the impact of process variation on 45 nm NoC-based CMPs es_ES
dc.type Artículo es_ES
dc.embargo.lift 10000-01-01
dc.embargo.terms forever es_ES
dc.identifier.doi 10.1016/j.jpdc.2010.09.006
dc.relation.projectID info:eu-repo/grantAgreement/MICINN//TIN2009-14475-C04-01/ES/Arquitecturas De Servidores, Aplicaciones Y Servicios/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/EC/FP7/248972/EU/Nanoscale Silicon-Aware Network-on-Chip Design Platform/ es_ES
dc.relation.projectID info:eu-repo/grantAgreement/MEC//CSD2006-00046/ES/Arquitecturas fiables y de altas prestaciones para centros de proceso de datos y servidores de Internet/ es_ES
dc.rights.accessRights Cerrado es_ES
dc.contributor.affiliation Universitat Politècnica de València. Departamento de Informática de Sistemas y Computadores - Departament d'Informàtica de Sistemes i Computadors es_ES
dc.contributor.affiliation Universitat Politècnica de València. Grupo de Arquitecturas Paralelas es_ES
dc.description.bibliographicCitation Hernández Luz, C.; Roca Pérez, A.; Flich Cardo, J.; Silla Jiménez, F.; Duato Marín, JF. (2011). Characterizing the impact of process variation on 45 nm NoC-based CMPs. Journal of Parallel and Distributed Computing. 71(5):651-663. https://doi.org/10.1016/j.jpdc.2010.09.006 es_ES
dc.description.accrualMethod S es_ES
dc.relation.publisherversion http://dx.doi.org/10.1016/j.jpdc.2010.09.006 es_ES
dc.description.upvformatpinicio 651 es_ES
dc.description.upvformatpfin 663 es_ES
dc.type.version info:eu-repo/semantics/publishedVersion es_ES
dc.description.volume 71 es_ES
dc.description.issue 5 es_ES
dc.relation.senia 207769
dc.contributor.funder European Commission
dc.contributor.funder Ministerio de Ciencia e Innovación
dc.contributor.funder Ministerio de Educación y Ciencia es_ES


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