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Speed optimization of a multilayer-board for multi-gigabit/s chip-to-chip interconnects

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Speed optimization of a multilayer-board for multi-gigabit/s chip-to-chip interconnects

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Pleite Moreno, C. (2011). Speed optimization of a multilayer-board for multi-gigabit/s chip-to-chip interconnects. http://hdl.handle.net/10251/11506.

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Title: Speed optimization of a multilayer-board for multi-gigabit/s chip-to-chip interconnects
Author:
Director(s): Corral González, Juan Luis
UPV Unit: Universitat Politècnica de València. Escuela Politécnica Superior de Gandia - Escola Politècnica Superior de Gandia
Read date / Event date:
2011-06-06
Issued date:
Abstract:
The main aim of this project is to increase the data rate communication between a CPU and a DRAM to above 6.5 GHz by optimization of the Printed Circuit Board (PCB) interconnections (these interconnections include vias, ...[+]
Copyrigths: Reserva de todos los derechos
degree: Ingeniero Técnico de Telecomunicación, esp. en Sistemas de Telecomunicación-Enginyer Tècnic de Telecomunicació, esp. en Sistemes de Telecomunicacions
Type: Proyecto/Trabajo fin de carrera/grado

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